On 25/04/14 17:37, Adhyas Avasthi wrote: > Quick question on SMMU for device isolation. Is this for isolation > for accesses from CPU cores to devices, or can SMMU also provide No. This is what MMU at Stage-2 does. Isolation in this context is about restricting accesses from bus-mastering devices to memory or other slaves. > isolation for DMA operations from the device to physical memory (like > what IOMMU provides) to safeguard against faulty writes ? Assuming we have an SMMU offering nested translations, we end-up with the same configuration as we have on the CPU side: - Stage-2 define the same IPA-PA as we have on the CPU side (a "virtual physical" address space), controlled by the hypervisor. - Stage-1 is what the guest decides to program for its DMA operations. M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
