On 10 April 2014 20:41, Rob Herring <robherring2@xxxxxxxxx> wrote: > On Thu, Apr 10, 2014 at 10:02 AM, Peter Maydell > <peter.maydell@xxxxxxxxxx> wrote: >> We could in theory write an a57mpcore_priv which was a >> carbon copy of a15mpcore_priv, but that seems a bit pointless. >> I think it's probably actually reasonable to use a15mpcore_priv >> here, with an appropriate comment: >> >> /* Our A57 has an A15-style GICv2, so we can use a15mpcore_priv */ > > I think there are 3 possibilities of what actual h/w may look like. i > agree this is the correct thing to do for one case (and is the only > one qemu is able to support today). The others are: > > A57 + SBSA compliant GICv2(M) > A57 + GICv3 > > The SBSA change is making each register bank within the GIC 64K spaced > instead of 4K spaced to support 64KB pages in OSs and hypervisors. That part is pretty easy to do in QEMU -- we'd just need a suitable container object that mapped the GIC regions in different locations. It might be worth doing that now rather than putting this in and then changing it later. > This is a simple address swizzling trick defined in the SBSA doc. > (Since it's documented it must not be a cute embedded nonsense hack. > :)) Then the M portion is for PCI MSI support which is optional. I haven't looked too closely at the GICv2M spec but it probably is not too hard (certainly in comparison to the v3 GIC ;-)) thanks -- PMM _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm