On 31 January 2014 15:45, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote: > Review appreciated, especially for the early patches in the > series and for the accessfn refactoring, so I can start to > feed these patches into target-arm.next. OK, I'm going to put a bunch of the groundwork/cpreg API refactoring patches into target-arm.next. Specifically: > Peter Maydell (35): > target-arm: Fix raw read and write functions on AArch64 registers This patch was broken and needs a respin > target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs > target-arm: Define names for SCTLR bits > target-arm: Restrict check_ap() use of S and R bits to v6 and earlier > target-arm: Remove unused ARMCPUState sr substruct > target-arm: Log bad system register accesses with LOG_UNIMP these were fine and got review (mostly) -- will put in target-arm.next > target-arm: Add exception level to the AArch64 TB flags > target-arm: A64: Implement store-exclusive for system mode > target-arm: A64: Implement MSR (immediate) instructions will skip these for now (either unreviewed or have issues) > target-arm: Stop underdecoding ARM946 PRBS registers > target-arm: Split cpreg access checks out from read/write functions > target-arm: Convert performance monitor reginfo to accesfn > target-arm: Convert generic timer reginfo to accessfn > target-arm: Convert miscellaneous reginfo structs to accessfn > target-arm: Drop success/fail return from cpreg read and write > functions > target-arm: Remove unnecessary code now read/write fns can't fail > target-arm: Remove failure status return from read/write_raw_cp_reg > target-arm: Fix incorrect type for value argument to write_raw_cp_reg these were all reviewed so will go into target-arm.next > target-arm: A64: Make cache ID registers visible to AArch64 > target-arm: Implement AArch64 CurrentEL sysreg > target-arm: Implement AArch64 MIDR_EL1 > target-arm: Implement AArch64 DAIF system register > target-arm: Implement AArch64 cache invalidate/clean ops > target-arm: Implement AArch64 TLB invalidate ops > target-arm: Implement AArch64 dummy MDSCR_EL1 > target-arm: Implement AArch64 memory attribute registers > target-arm: Implement AArch64 SCTLR_EL1 > target-arm: Implement AArch64 TCR_EL1 > target-arm: Implement AArch64 VBAR_EL1 > target-arm: Implement AArch64 TTBR* > target-arm: Implement AArch64 MPIDR > target-arm: Implement AArch64 generic timers > target-arm: Implement AArch64 ID and feature registers > target-arm: Implement AArch64 dummy breakpoint and watchpoint > registers > target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI These were mostly fine (some review issues to be addressed) but they depend on a fixed version of that patch at the top of the stack so won't put them in for now; will retransmit in a v2 series. thanks -- PMM _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
