On 22 January 2014 03:10, Hu Tao <hutao@xxxxxxxxxxxxxx> wrote:
> On Tue, Jan 21, 2014 at 08:12:14PM +0000, Peter Maydell wrote:
>> + /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
>> + * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
>> + * to catch that case at translate time.
>> + */
>> + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
>> + raise_exception(env, EXCP_UDEF);
>
> Not sure EXCP_UDEF is correct here. In this case we are trapped from EL0
> to EL1, and setting EC to 0x00 if ESR_EL1 is implemented.
It's our closest current available exception and is what we've been
using consistently for other bad-sysreg access exceptions.
You are correct that for the full AArch64 system model we need
to fix exception handling and provide a syndrome register value
for every place we take an exception. That will come in a later
patchset.
thanks
-- PMM
_______________________________________________
kvmarm mailing list
kvmarm@xxxxxxxxxxxxxxxxxxxxx
https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
