On Tue, Jan 21, 2014 at 08:12:14PM +0000, Peter Maydell wrote:
> Implement the MSR (immediate) instructions, which can update the
> PSTATE SP and DAIF fields.
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper.h | 2 ++
> target-arm/op_helper.c | 25 +++++++++++++++++++++++++
> target-arm/translate-a64.c | 24 +++++++++++++++++++++++-
> 4 files changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 1966a19..1dce28b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -431,6 +431,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
> #define PSTATE_Z (1U << 30)
> #define PSTATE_N (1U << 31)
> #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
> +#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
> #define CACHED_PSTATE_BITS (PSTATE_NZCV)
> /* Mode values for AArch64 */
> #define PSTATE_MODE_EL3h 13
> diff --git a/target-arm/helper.h b/target-arm/helper.h
> index 70872df..638c91a 100644
> --- a/target-arm/helper.h
> +++ b/target-arm/helper.h
> @@ -62,6 +62,8 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
> DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
> DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
>
> +DEF_HELPER_3(msr_i_pstate, void, env, i32, i32)
> +
> DEF_HELPER_2(get_r13_banked, i32, env, i32)
> DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index a918e5b..c812a9f 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -313,6 +313,31 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
> return value;
> }
>
> +void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
> +{
> + /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
> + * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
> + * to catch that case at translate time.
> + */
> + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
> + raise_exception(env, EXCP_UDEF);
Not sure EXCP_UDEF is correct here. In this case we are trapped from EL0
to EL1, and setting EC to 0x00 if ESR_EL1 is implemented.
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