On 05/06/13 08:31, Zhaobo (Bob, ERC) wrote:
> Hi Christoffer,
> I discussed with marc before ,current implementation of vgic doesn't fully comply with ARM gic specs ,SPI distribution is one among them.
> In the spec it is allowed to configure one SPI to several target cpu interfaces , and let the OS to leverage the cpu workload.
> But in the source code , one SPI only bind to one specific cpu interface via LSB method (see function vgic_set_target_reg).
> for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
> int shift = i * GICD_CPUTARGETS_BITS;
> target = ffs((val >> shift) & 0xffU);
> target = target ? (target - 1) : 0;
> dist->irq_spi_cpu[irq + i] = target;
> kvm_for_each_vcpu(c, vcpu, kvm) {
> bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
> if (c == target)
> set_bit(irq + i, bmap);
> else
> clear_bit(irq + i, bmap);
> }
> }
> That is why I create this patch for vgic_get_target_reg to get the only one cpu number we set before .
>
> I don't know whether it is a issue for SMP mode linux. But it do simplify the implementation of OS layer.
SMP Linux works just fine (and actually only set a single bit in the
GICC_ITARGETRn registers). As we don't use or even implement priority
support, what would be the benefit of supporting multiple target CPUs?
Now, if you have an example of a publicly available guest that
demonstrably fails with the current VGIC implementation, I'm happy to
investigate supporting the missing features.
Until then, things are unlikely to change.
M.
--
Jazz is not dead. It just smells funny...
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