Am 17.03.2013 um 15:43 schrieb Will Deacon <will.deacon@xxxxxxx>: > Hi Alex, > > I've been away from my box for a bit, so sorry for the delay. Heh, yeah, Marc already indicated that :) > > On Thu, Mar 14, 2013 at 12:13:52PM +0000, Alexander Graf wrote: >>> Does anyone have an idea how to debug this? Will mentioned TLB breakage that he had a branch for, so I'm going to try his branch next as guest kernel. >> >> Ok, so Will's branch is based on 3.8, which means I don't have mach_virt or Arndale support in there. Merging that branch into 3.9 myself would probably introduce more breakage than it fixes :). >> >> So Will, could you please take that branch up to 3.9? I'll give it a try then :). > > Sure, I'll bring things up to speed tomorrow. Marc did that for me already :). It didn't help. > In the meantime, the fact that > disabling ASLR makes your problem disappear *is* indicative of TLB problems, > it means that when you end up accessing the wrong address space the page > you're after happens to be mapped (with ASLR, you're more likely to fault). Turns out, ASLR really doesn't change this for real. I managed to boil down the breakage to a simple cc1 call that some times ends up segfaulting with pc=NULL after a pc-relative bl instruction. I gave Marc an image that I can reliably reproduce it with. I'm actually assuming a CPU core bug by now. Could you please check A15 errata for anything that sounds like this? Alex > > You might want to check how much you've miscompiled :) > > Will _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
