[PATCH 2/3] KVM: ARM: Swap CCSIDR.

[Rusty Russell <rusty.russell@xxxxxxxxxx>]

We need to save and restore it.

Signed-off-by: Rusty Russell <rusty.russell@xxxxxxxxxx>

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 824c9be..c2b3dfe 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -100,6 +100,7 @@ enum vcpu_mode {
 /* 0 is reserved as an invalid value. */
 enum cp15_regs {
 	c0_MPIDR=1,		/* MultiProcessor ID Register */
+	c0_CSSELR,		/* Cache Size Selection Register */
 	c1_SCTLR,		/* System Control Register */
 	c1_ACTLR,		/* Auxilliary Control Register */
 	c1_CPACR,		/* Coprocessor Access Control */
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index c1b4bb9..b277b7a 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -149,6 +149,7 @@ int main(void)
   DEFINE(VCPU_KVM,		offsetof(struct kvm_vcpu, kvm));
   DEFINE(VCPU_MIDR,		offsetof(struct kvm_vcpu, arch.midr));
   DEFINE(VCPU_MPIDR,		offsetof(struct kvm_vcpu, arch.cp15[c0_MPIDR]));
+  DEFINE(VCPU_CSSELR,		offsetof(struct kvm_vcpu, arch.cp15[c0_CSSELR]));
   DEFINE(VCPU_SCTLR,		offsetof(struct kvm_vcpu, arch.cp15[c1_SCTLR]));
   DEFINE(VCPU_CPACR,		offsetof(struct kvm_vcpu, arch.cp15[c1_CPACR]));
   DEFINE(VCPU_TTBR0,		offsetof(struct kvm_vcpu, arch.cp15[c2_TTBR0]));
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index d6ff1e9..894840d 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -333,6 +333,10 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
  * Important: Must sorted ascending by CRn, CRM, Op1, Op2
  */
 static const struct coproc_reg cp15_regs[] = {
+	/* CSSELR: swapped by interrupt.S. */
+	{ CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
+			NULL, reset_unknown, c0_CSSELR },
+
 	/* TTBR0/TTBR1: swapped by interrupt.S. */
 	{ CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
 	{ CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index 1c8d627..60768bf 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -200,9 +200,10 @@ ENDPROC(__kvm_flush_vm_context)
 	mrrc	p15, 1, r8, r9, c2	@ TTBR 1
 	mrc	p15, 0, r10, c10, c2, 0	@ PRRR
 	mrc	p15, 0, r11, c10, c2, 1	@ NMRR
+	mrc	p15, 2, r12, c0, c0, 0	@ CSSELR
 
 	.if \vcpu == 0
-	push	{r2-r11}		@ Push CP15 registers
+	push	{r2-r12}		@ Push CP15 registers
 	.else
 	str	r2, [\vcpup, #VCPU_SCTLR]
 	str	r3, [\vcpup, #VCPU_CPACR]
@@ -215,6 +216,7 @@ ENDPROC(__kvm_flush_vm_context)
 	sub	\vcpup, \vcpup, #(VCPU_TTBR1)
 	str	r10, [\vcpup, #VCPU_PRRR]
 	str	r11, [\vcpup, #VCPU_NMRR]
+	str	r12, [\vcpup, #VCPU_CSSELR]
 	.endif
 
 	mrc	p15, 0, r2, c13, c0, 1	@ CID
@@ -281,7 +283,7 @@ ENDPROC(__kvm_flush_vm_context)
 	mcr	p15, 0, r12, c12, c0, 0	@ VBAR
 
 	.if \vcpu == 0
-	pop	{r2-r11}
+	pop	{r2-r12}
 	.else
 	ldr	r2, [\vcpup, #VCPU_SCTLR]
 	ldr	r3, [\vcpup, #VCPU_CPACR]
@@ -294,6 +296,7 @@ ENDPROC(__kvm_flush_vm_context)
 	sub	\vcpup, \vcpup, #(VCPU_TTBR1)
 	ldr	r10, [\vcpup, #VCPU_PRRR]
 	ldr	r11, [\vcpup, #VCPU_NMRR]
+	ldr	r12, [\vcpup, #VCPU_CSSELR]
 	.endif
 
 	mcr	p15, 0, r2, c1, c0, 0	@ SCTLR
@@ -304,6 +307,7 @@ ENDPROC(__kvm_flush_vm_context)
 	mcrr	p15, 1, r8, r9, c2	@ TTBR 1
 	mcr	p15, 0, r10, c10, c2, 0	@ PRRR
 	mcr	p15, 0, r11, c10, c2, 1	@ NMRR
+	mcr	p15, 2, r12, c0, c0, 0	@ CSSELR
 .endm
 
 /*
_______________________________________________
kvmarm mailing list
kvmarm@xxxxxxxxxxxxxxxxxxxxx
https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm