On Thu, Jul 12, 2012 at 7:54 AM, Rusty Russell <rusty.russell@xxxxxxxxxx> wrote:
> These registers are defined to be WO, meaning reads are unpredicable.
> Unless some actual guest breaks, it's most friendly to fall though and
> inject an undefined exception.
>
agreed, only issue is, that if we don't have any handler function for
this, then we print to the host kernel log indicating that something
is missing, but while writing this I realize it's fixed in the
access_dcsw function which makes this commit a funny kind of no-op
that I can definitely merge on the path to eternal cp15 glory ;)
> Signed-off-by: Rusty Russell <rusty@xxxxxxxxxxxxxxx>
> ---
> arch/arm/kvm/emulate.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
> index e6db0f2..7b0fde1 100644
> --- a/arch/arm/kvm/emulate.c
> +++ b/arch/arm/kvm/emulate.c
> @@ -358,11 +358,8 @@ static const struct coproc_emulate coproc_emulate[] = {
> * DC{C,I,CI}SW operations:
> */
> { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, WRITE, write_dcsw},
> - { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, READ, read_zero},
> { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, WRITE, write_dcsw},
> - { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, READ, read_zero},
> { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, WRITE, write_dcsw},
> - { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, READ, read_zero},
> /*
> * L2CTLR access (guest wants to know #CPUs).
> *
> --
> 1.7.9.5
>
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