Re: [PATCH 02/17] ARM: KVM: Pass-through CRn = 10 CP15 accesses from guest.

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On Thu, Jul 12, 2012 at 7:54 AM, Rusty Russell <rusty.russell@xxxxxxxxxx> wrote:
> We already save and restore the NMRR and PRRR registers on
> worldswitch, and the A15 has nothing else that is interesting in that
> range (in particular, it doesn't have TLB lockdown).
>
> Note: the A9 has TLB lockdown there, so if we wanted to emulate one of
> those accurately we'd need this, but that's currently out-of-scope.
>
> Signed-off-by: Rusty Russell <rusty@xxxxxxxxxxxxxxx>
> ---
>  arch/arm/kvm/emulate.c    |   26 --------------------------
>  arch/arm/kvm/interrupts.S |    4 ++--
>  2 files changed, 2 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
> index df00760..e6db0f2 100644
> --- a/arch/arm/kvm/emulate.c
> +++ b/arch/arm/kvm/emulate.c
> @@ -319,17 +319,6 @@ static bool write_dcsw(struct kvm_vcpu *vcpu,
>         return true;
>  }
>
> -static bool access_cp15_reg(struct kvm_vcpu *vcpu,
> -                           const struct coproc_params *p,
> -                           unsigned long cp15_reg)
> -{
> -       if (p->is_write)
> -               vcpu->arch.cp15[cp15_reg] = *vcpu_reg(vcpu, p->Rt1);
> -       else
> -               *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[cp15_reg];
> -       return true;
> -}
> -
>  /* Any field which is 0xFFFFFFFF == DF */
>  struct coproc_emulate {
>         unsigned long CRn;
> @@ -386,21 +375,6 @@ static const struct coproc_emulate coproc_emulate[] = {
>         { CRn( 9), CRm(DF), Op1(DF), Op2(DF), is32,  READ,  read_zero},
>
>         /*
> -        * These CRn == 10 entries may not need to exist - if we can
> -        * ignore guest attempts to tamper with TLB lockdowns then it
> -        * should be enough to store/restore the host/guest PRRR and
> -        * NMRR memory remap registers and allow guest direct access
> -        * to these registers.
> -        *
> -        * TLB Lockdown operations - ignored
> -        */
> -       { CRn(10), CRm( 0), Op1(DF), Op2(DF), is32,  WRITE, ignore_write},
> -       { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,  RW,    access_cp15_reg,
> -                                                           c10_PRRR},
> -       { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,  RW,    access_cp15_reg,
> -                                                           c10_NMRR},
> -
> -       /*
>          * The CP15 c15 register is architecturally implementation
>          * defined, but some guest kernels attempt to read/write a
>          * diagnostics register here. We always return 0 and ignore
> diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
> index 6e1e12d..c7aa96a 100644
> --- a/arch/arm/kvm/interrupts.S
> +++ b/arch/arm/kvm/interrupts.S
> @@ -409,9 +409,9 @@ ENDPROC(__kvm_flush_vm_context)
>   * (hardware reset value is 0) */
>  .macro set_hstr entry
>         mrc     p15, 4, r2, c1, c1, 3
> -       ldr     r3, =(HSTR_T(9) | HSTR_T(10) | HSTR_T(11) | HSTR_T(15))
> +       ldr     r3, =(HSTR_T(9) | HSTR_T(11) | HSTR_T(15))
>         .if \entry == 1
> -       orr     r2, r2, r3              @ Trap CR{9,10,11,15}
> +       orr     r2, r2, r3              @ Trap CR{9,11,15}
>         .else
>         bic     r2, r2, r3              @ Don't trap any CRx accesses
>         .endif
> --
> 1.7.9.5
>
thanks, applied.
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