FYI ---------- Forwarded message ---------- From: Christoffer Dall <c.dall at virtualopensystems.com> Date: Wed, Jun 13, 2012 at 11:54 PM Subject: Re: test out an assumption To: Rusty Russell <rusty at rustcorp.com.au> Cc: Marc Zyngier <marc.zyngier at arm.com> On Wed, Jun 13, 2012 at 11:01 PM, Rusty Russell <rusty at rustcorp.com.au> wrote: > On Wed, 13 Jun 2012 19:10:41 -0400, Christoffer Dall <c.dall at virtualopensystems.com> wrote: >> Hi Marc (and Rusty), >> >> when we capture the IPA of the offending instruction for data aborts >> where the ISS is not valid, remember that there was this annoying >> corner case where a 4 byte wide thumb instruction could be aligned at >> the last 2 bytes of a PAGE and therefore we will need both pages. In >> this case, easy enough, we can get the second IPA and be able to fully >> decode the instruction, but then I am thinking about the validity of >> the following page. >> >> My reasoning is that if we got the data abort in the first case, the >> CPU must have been able to decode the load/store instruction, and >> therefore both pages must be valid and we can safely call the ATS1CPR >> operation for both pages. > > Good point. ?But if there are two guest vcpus, can the map change in the > meantime? ?I think in theory it can, but we can do whatever we want with > that, as long as we don't crash the host :) > yeah, I guess it can, but that would usually involve at least some TLB flush or something, so seems unlikely. ?Of course, another CPU could change the stage2 mapping, by for example reclaiming a page, but we should handle that with copy_from_user. Everything we don on the host should be safe. (Did you just find a subtle corner case in the solution to the subtle corner case? :) How do you do it?) >> However, we don't know at this point how >> wide the instruction is and therefor just have to perform the >> translation. ?This is information is useful later at decoding time >> though, when we are then sure that there must be a readable page >> containing the last two bytes of the instruction. >> >> If I read the specifications right, the ATS1CPR operation performed by >> Hyp mode never causes an abort, but just sets the validity bit in the >> PAR that we must remember to check and we can therefore safely perform >> the operation in the exception handler. > > I agree with that reading. > Thanks! -Christoffer
