On Fri, Nov 30, 2007 at 12:59:26AM -0800, Yinghai Lu wrote: > On Nov 29, 2007 6:54 PM, Eric W. Biederman <ebiederm at xmission.com> wrote: > > Ben Woodard <woodard at redhat.com> writes: > > > > > > > Eric W. Biederman wrote: > > >> Vivek Goyal <vgoyal at redhat.com> writes: > > >> > > >>> Ok. Got it. So in this case we route the interrupts directly through LAPIC > > >>> and put LVT0 in ExtInt mode and IOAPIC is bypassed. > > >>> > > >>> I am looking at Intel Multiprocessor specification v1.4 and as per figure > > >>> 3-3 on page 3-9, 8259 is connected to LINTIN0 line, which in turn is > > >>> connected to LINTIN0 pin on all processors. If that is the case, even in > > >>> this mode, all the CPU should see the timer interrupts (which is coming > > >>> from 8259)? > > >> > > there is two mode for mcp55. bios should have one option about virtul > wired to LVT0 of BSP or IOAPIC pin 0. > or the option like hpet route to ioapic pin 2. > That's interesting. So with BIOS options I can force timer interrupts to be routed through IOAPIC? That would enable us to get timer interrupts on any of the cpus in legacy mode. Ben, can you give it a try? > for kdump fix, could enable LVT0 of CPU for kdump and disable that for BSP? We would not know the crashing cpu in advance hence can't set it. Thanks Vivek
