On Tue, May 05, 2020 at 11:44:06AM +0100, Will Deacon wrote: > Catalin -- did you get anything back from the architects about the cache > hit behaviour? Any read from a non-cacheable alias would be coherent with writes using the same non-cacheable attributes, irrespective of other cacheable aliases (of course, subject to the cache lines having been previously cleaned/invalidated to avoid dirty lines evictions). So as long as the hardware works as per the ARM ARM (B2.8), we don't need to unmap the non-cacheable DMA buffers from the linear map. -- Catalin
