On Fri, Apr 03, 2020 at 10:58:51AM +0200, Ard Biesheuvel wrote: > On Thu, 2 Apr 2020 at 13:30, Catalin Marinas <catalin.marinas@xxxxxxx> wrote: > > On Mon, Mar 30, 2020 at 04:32:31PM +0200, Ard Biesheuvel wrote: > > > On Mon, 30 Mar 2020 at 16:28, Will Deacon <will@xxxxxxxxxx> wrote: > > > > Fair enough, but I'd still like to see some numbers. If they're compelling, > > > > then we could explore something like CONFIG_OF_DMA_DEFAULT_COHERENT, but > > > > that doesn't really help the kconfig maze :( > > > > I'd prefer not to have a config option, we could easily break single > > Image at some point. > > > > > Could we make this a runtime thing? E.g., remap the entire linear > > > region down to pages under stop_machine() the first time we probe a > > > device that uses non-coherent DMA? > > > > That could be pretty expensive at run-time. With the ARMv8.4-TTRem > > feature, I wonder whether we could do this lazily when allocating > > non-coherent DMA buffers. > > > > (I still hope there isn't a problem at all with this mismatch ;)). > > > > Now that we have the pieces to easily remap the linear region down to > pages, and [apparently] some generic infrastructure to manage the > linear aliases, the only downside is the alleged performance hit > resulting from increased TLB pressure. This is obviously highly > micro-architecture dependent, but with Xgene1 and ThunderX1 out of the > picture, I wonder if the tradeoffs are different now. Maybe by now, we > should just suck it up (Note that we had no complaints afaik regarding > the fact that we map the linear map down to pages by default now) I'd be in favour of that fwiw. Catalin -- did you get anything back from the architects about the cache hit behaviour? Will
