Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> Select idle frequency during initialisation, then reset the last known
> frequency when re-enabling. This allows us to preserve the user selected
> frequency across resets.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 34 +++++++++++++++++-----------------
> 1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 658a75659657..98f0afa08332 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5092,6 +5092,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> }
>
> dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
> + dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
>
> /* Preserve min/max settings in case of re-init */
> if (dev_priv->rps.max_freq_softlimit == 0)
> @@ -5108,6 +5109,15 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void reset_rps(struct drm_i915_private *dev_priv,
> + void (*set)(struct drm_i915_private *, u8))
> +{
> + u8 freq = dev_priv->rps.cur_freq; /* force a reset */
> + dev_priv->rps.power = -1;
I didn't find a spot where rps.power == -1 would cause
a reset.
For me it seems that gen6_init_rps_frequencies only handles
the enums thus with -1 we never will update the rps.power.
-Mika
> + dev_priv->rps.cur_freq = -1;
> + set(dev_priv, freq);
> +}
> +
> /* See the Gen9_GT_PM_Programming_Guide doc for the below */
> static void gen9_enable_rps(struct drm_i915_private *dev_priv)
> {
> @@ -5144,8 +5154,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
> /* Leaning on the below call to gen6_set_rps to program/setup the
> * Up/Down EI & threshold registers, as well as the RP_CONTROL,
> * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
> - dev_priv->rps.power = HIGH_POWER; /* force a reset */
> - gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
> + reset_rps(dev_priv, gen6_set_rps);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
> @@ -5291,8 +5300,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
>
> /* 6: Ring frequency + overclocking (our driver does this later */
>
> - dev_priv->rps.power = HIGH_POWER; /* force a reset */
> - gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
> + reset_rps(dev_priv, gen6_set_rps);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
> @@ -5385,8 +5393,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> dev_priv->rps.max_freq = pcu_mbox & 0xff;
> }
>
> - dev_priv->rps.power = HIGH_POWER; /* force a reset */
> - gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
> + reset_rps(dev_priv, gen6_set_rps);
>
> rc6vids = 0;
> ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> @@ -5750,6 +5757,7 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
> dev_priv->rps.min_freq);
>
> dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
> + dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
>
> /* Preserve min/max settings in case of re-init */
> if (dev_priv->rps.max_freq_softlimit == 0)
> @@ -5814,6 +5822,7 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
> "Odd GPU freq values\n");
>
> dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
> + dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
>
> /* Preserve min/max settings in case of re-init */
> if (dev_priv->rps.max_freq_softlimit == 0)
> @@ -5922,7 +5931,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
> intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
> dev_priv->rps.idle_freq);
>
> - valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
> + reset_rps(dev_priv, valleyview_set_rps);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
> @@ -6002,16 +6011,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
> DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>
> - dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> - DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> - intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> - dev_priv->rps.cur_freq);
> -
> - DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> - intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
> - dev_priv->rps.idle_freq);
> -
> - valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
> + reset_rps(dev_priv, valleyview_set_rps);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
> --
> 2.8.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
