On Thu, Jun 09, 2016 at 03:14:54PM -0700, Matt Roper wrote:
> When we sanitize our DDB and watermark info during the first atomic
> commit, we need to calculate the total data rate. Since we haven't
> explicitly added the planes for each CRTC to our atomic state, the total
> data rate calculation will try to use the cached values from a previous
> commit (which are 0 since there was no previous commit); this result is
> incorrect if we inherited any active planes from the BIOS.
>
> During our very first atomic commit, we need to explicitly add all
> active planes to the atomic state to ensure that valid data rate values
> are calculated for them. Subsequent commits will then have valid cached
> values to fall back on.
>
> Reported-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0cd38ca..ba08639 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3933,6 +3933,18 @@ skl_compute_ddb(struct drm_atomic_state *state)
> if (IS_ERR(cstate))
> return PTR_ERR(cstate);
>
> + /*
> + * If this is our first commit after hw readout, we don't have
> + * valid data rate values cached. Add all planes to ensure we
> + * calculate a valid data rate.
> + */
> + if (dev_priv->wm.distrust_bios_wm) {
> + ret = drm_atomic_add_affected_planes(state,
> + &intel_crtc->base);
Again, imo should be pulled out. Other wm code probably has the exact same
bug.
-Daniel
> + if (ret)
> + return ret;
> + }
> +
> ret = skl_allocate_pipe_ddb(cstate, ddb);
> if (ret)
> return ret;
> --
> 2.1.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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