On Mon, 2016-05-16 at 16:59 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Like with cdclk, the DMC is supposed to manage dbuf enabling/disabling.
> Let's make sure it has correctly restored the dbuf state to enabled
> when we disable the DC states.
>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Suggested-by: Imre Deak <imre.deak@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b70e123f67ca..27cb92c18bb5 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -806,6 +806,15 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> }
>
> +static void skl_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
I would've used gen9_ prefix. Either way:
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> +{
> + u32 tmp = I915_READ(DBUF_CTL);
> +
> + WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
> + (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
> + "Unexpected DBuf power power state (0x%08x)\n", tmp);
> +}
> +
> static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -814,6 +823,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> WARN_ON(dev_priv->cdclk_freq !=
> dev_priv->display.get_display_clock_speed(dev_priv->dev));
>
> + skl_assert_dbuf_enabled(dev_priv);
> +
> if (IS_BROXTON(dev_priv))
> broxton_ddi_phy_verify_state(dev_priv);
> }
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