On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> In case the driver is initialized without active displays, we should
> just drop the cdclk to the minimum frequency right off the bat. There
> might not be a modeset to drop it to the minimum late rafter all.
>
> With DMC supposedly we should always have the cdclk up and running.
> The DMC will shut the DE PLL down when appropriate, so let's nuke
> the related FIXMEs as well. Trying to do anything different would
> go against the expectations of the DMC firmware, and we all know
> how fragile the DMC firmware is.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9725ba59716e..ac8d448e96d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -118,6 +118,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
> static void intel_modeset_setup_hw_state(struct drm_device *dev);
> static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
> static int ilk_max_pixel_rate(struct drm_atomic_state *state);
> +static int broxton_calc_cdclk(int max_pixclk);
>
> struct intel_limit {
> struct {
> @@ -5501,10 +5502,8 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
> * FIXME:
> * - The initial CDCLK needs to be read from VBT.
> * Need to make this change after VBT has changes for BXT.
> - * - check if setting the max (or any) cdclk freq is really necessary
> - * here, it belongs to modeset time
> */
> - broxton_set_cdclk(dev_priv, 624000);
> + broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));
> }
>
> void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
> @@ -5944,10 +5943,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>
> static int broxton_calc_cdclk(int max_pixclk)
> {
> - /*
> - * FIXME:
> - * - set 19.2MHz bypass frequency if there are no active pipes
> - */
> if (max_pixclk > 576000)
> return 624000;
> else if (max_pixclk > 384000)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
