Thanks Jani A customer of mine decided to work with a modified DP port with only two lanes and is facing issues. I guess modifying the suggested values might be useful at O.S leve, however I was wondering if modifyint the register that I mentioned earlier in the VBIOS would accomplish the same for the pre-OS stage. Best Regards, Adolfo Sanchez -----Original Message----- From: Jani Nikula [mailto:jani.nikula@xxxxxxxxxxxxxxx] Sent: Wednesday, May 18, 2016 12:38 AM To: Sanchez, AdolfoX <adolfox.sanchez@xxxxxxxxx>; intel-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: Re: force DP lane count on Broadwell platform On Wed, 18 May 2016, "Sanchez, AdolfoX" <adolfox.sanchez@xxxxxxxxx> wrote: > What PRM registers should be modified to force the source lanes to > report 2 lanes maximum? Is it enough to modify the registers > DP_TP_CTL and DDI_BUF_CTL, or should any other register be modified? You should probably look at intel_ddi_init() in intel_ddi.c, and set intel_dig_port->max_lanes to 2. Then it should limit the source to two lanes wherever it's needed. Of course, I should ask you why you need this; maybe you should be asking a different question. ;) BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
