On Wed, 2016-05-11 at 22:44 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> We don't need any pixel clock vs. cdclk guardband since HSW. BXT still
> tries to add one though. Get rid of it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Matches "Gen9 Display Resolution Support" which only sets scaling
specific limits and doesn't mention the "90% rule" required by the IVB
"Pixel Rate Limitations":
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9564719b53e3..57ff51172065 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5905,16 +5905,15 @@ static int broxton_calc_cdclk(int max_pixclk)
> {
> /*
> * FIXME:
> - * - remove the guardband, it's not needed on BXT
> * - set 19.2MHz bypass frequency if there are no active pipes
> */
> - if (max_pixclk > 576000*9/10)
> + if (max_pixclk > 576000)
> return 624000;
> - else if (max_pixclk > 384000*9/10)
> + else if (max_pixclk > 384000)
> return 576000;
> - else if (max_pixclk > 288000*9/10)
> + else if (max_pixclk > 288000)
> return 384000;
> - else if (max_pixclk > 144000*9/10)
> + else if (max_pixclk > 144000)
> return 288000;
> else
> return 144000;
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