On Mon, Apr 25, 2016 at 03:38:05PM +0300, Imre Deak wrote: > BSpec requires us to wait ~100 clocks before re-enabling clock gating, > so make sure we do this. > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 702f683..a6fd4dd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6711,6 +6711,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev) > misccpctl = I915_READ(GEN7_MISCCPCTL); > I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); > I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); > + /* > + * Wait at least 100 clocks before re-enabling clock gating. See > + * the definition of L3SQCREG1 in BSpec. > + */ > + POSTING_READ(GEN8_L3SQCREG1); > + udelay(1); > I915_WRITE(GEN7_MISCCPCTL, misccpctl); > > /* > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
