On Thu, Apr 21, 2016 at 05:49:52PM -0400, Lyude Paul wrote:
> On a T560, this ends up rejecting valid watermark configurations so the internal
> display doesn't switch from fbcon to X properly:
Hmm. We can leave this patch out of the series and still have a fix for
the WARN_ON(!wm_changed), but one of the main goals was to identify and
reject configurations that the platform is truly incapable of handling.
I'm still going to include this patch in my next spin of the series on
the mailing list, but we can just omit it during merge if we need more
time to figure out why your configuration is being rejected. I'll also
add an extra DRM_DEBUG_KMS line to this patch to give us more insight
into what the final calculated values were and how far out of bounds
they were.
If you drop this patch but keep the rest of the series, does the system
still operate properly when it goes into X? I.e., no underruns reported
and no flickering/corruption on screen?
Could you provide the contents of
/sys/kernel/debug/dri/0/i915_pri_wm_latency ? I've heard that there are
some SKL pcode (BIOS) versions floating around that give bad memory
latency values which result in us calculating the wrong watermark values
in the end; it would be good to see if that's a contributing factor
here.
Also, I can see your eDP panel in the log below; is that your only
display or do you also have an external display attached?
Matt
>
> [ 5.767383] [drm:intelfb_create] re-using BIOS fb
> [ 5.767444] [drm] Initialized i915 1.6.0 20160411 for 0000:00:02.0 on minor 0
> [ 5.767449] [drm:intelfb_create] allocated 1920x1080 fb: 0x00000000, bo ffff88021374c000
> [ 5.767760] fbcon: inteldrmfb (fb0) is primary device
> [ 5.768147] [drm:connected_sink_compute_bpp] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
> [ 5.768150] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [ 5.768159] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26] scaler_user index 0.31
> [ 5.768162] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
> [ 5.768166] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 142900KHz
> [ 5.768172] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
> [ 5.768174] [drm:intel_dp_compute_config] DP link bw required 257220 available 432000
> [ 5.768180] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 18, dithering: 1
> [ 5.768193] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8800d5c11000 for pipe A
> [ 5.768200] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
> [ 5.768202] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [ 5.768206] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [ 5.768211] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 4994717, gmch_n: 8388608, link_m: 277484, link_n: 524288, tu: 64
> [ 5.768215] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [ 5.768217] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [ 5.768219] [drm:intel_dump_pipe_config] requested mode:
> [ 5.768226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 142900 1920 1968 2000 2082 1080 1082 1087 1144 0x48 0xa
> [ 5.768228] [drm:intel_dump_pipe_config] adjusted mode:
> [ 5.768234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 142900 1920 1968 2000 2082 1080 1082 1087 1144 0x48 0xa
> [ 5.768239] [drm:intel_dump_crtc_timings] crtc timings: 142900 1920 1968 2000 2082 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [ 5.768241] [drm:intel_dump_pipe_config] port clock: 270000
> [ 5.768244] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [ 5.768247] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
> [ 5.768251] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [ 5.768254] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [ 5.768256] [drm:intel_dump_pipe_config] ips: 0
> [ 5.768258] [drm:intel_dump_pipe_config] double wide: 0
> [ 5.768263] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ctrl1: 0x13, cfgcr1: 0x0, cfgcr2: 0x0
> [ 5.768266] [drm:intel_dump_pipe_config] planes on this crtc
> [ 5.768277] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled
> [ 5.768284] [drm:intel_dump_pipe_config] FB:58, fb = 1920x1080 format = 0x34325258
> [ 5.768285] [drm:intel_dump_pipe_config] scaler:-1 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
> [ 5.768290] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = -1
> [ 5.768295] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = -1
> [ 5.768309] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 0.0
> [ 5.768319] [drm:intel_find_shared_dpll] CRTC:26 allocated DPLL 0
> [ 5.768323] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
> [ 5.768327] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26] scaler_user index 0.31
> [ 5.768339] [drm:skl_compute_plane_wm] Requested display configuration exceeds system watermark limitations
> [ 5.768359] [drm:drm_fb_helper_hotplug_event]
> [ 5.768363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
> [ 5.768367] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
> [ 5.768786] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
> [ 5.769177] [drm:intel_dp_probe_oui] Branch OUI: 444615
> [ 5.769604] [drm:drm_edid_to_eld] ELD: no CEA Extension found
> [ 5.769611] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
> [ 5.769618] [drm:drm_mode_debug_printmodeline] Modeline 38:"1920x1080" 60 142900 1920 1968 2000 2082 1080 1082 1087 1144 0x48 0xa
> [ 5.769621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1]
> [ 5.769624] [drm:intel_dp_detect] [CONNECTOR:45:DP-1]
> [ 5.769628] [drm:intel_power_well_enable] enabling power well 2
> [ 5.769633] [drm:skl_set_power_well] Enabling power well 2
> [ 5.769659] [drm:intel_power_well_disable] disabling power well 2
> [ 5.769672] [drm:skl_set_power_well] Disabling power well 2
>
> On Tue, 2016-04-19 at 19:26 -0700, Matt Roper wrote:
> > If we can't find any valid level 0 watermark values for the requested
> > atomic transaction, reject the configuration before we try to start
> > programming the hardware.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> > 1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 59d4574..96ffd54 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3309,7 +3309,17 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> >
> > if (res_blocks >= ddb_allocation || res_lines > 31) {
> > *enabled = false;
> > - return 0;
> > +
> > + /*
> > + * If there are no valid level 0 watermarks, then we can't
> > + * support this display configuration.
> > + */
> > + if (level) {
> > + return 0;
> > + } else {
> > + DRM_DEBUG_KMS("Requested display configuration
> > exceeds system watermark limitations\n");
> > + return -EINVAL;
> > + }
> > }
> >
> > *out_blocks = res_blocks;
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
