On Wed, Apr 13, 2016 at 08:47:51PM +0300, Ander Conselvan de Oliveira wrote:
> The code used by the DP and HDMI paths was very similar, so make them
> share it. Note that this removes the write to signal level registers
> from the HDMI pre pll enable path, but that's OK since those are set
> in vlv_hdmi_pre_enable() function.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Reviewed-by: Jim Bride <jim.bride@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 25 +------------------------
> drivers/gpu/drm/i915/intel_dpio_phy.c | 28 ++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_hdmi.c | 28 +---------------------------
> 4 files changed, 31 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f2481a2..a002870 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3568,6 +3568,7 @@ void chv_phy_post_disable(struct intel_encoder *encoder);
> void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> u32 demph_reg_value, u32 preemph_reg_value,
> u32 uniqtranscale_reg_value, u32 tx3_demph);
> +void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
>
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3e42355..4829ba9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2821,32 +2821,9 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
>
> static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
> {
> - struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc =
> - to_intel_crtc(encoder->base.crtc);
> - enum dpio_channel port = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
> -
> intel_dp_prepare(encoder);
>
> - /* Program Tx lane resets to default */
> - mutex_lock(&dev_priv->sb_lock);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> - DPIO_PCS_TX_LANE2_RESET |
> - DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> - DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> - DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> - (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> - DPIO_PCS_CLK_SOFT_RESET);
> -
> - /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_phy_pre_pll_enable(encoder);
> }
>
> static void chv_pre_enable_dp(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index d9e6482..846f35f 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -395,3 +395,31 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> mutex_unlock(&dev_priv->sb_lock);
> }
> +
> +void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(encoder->base.crtc);
> + enum dpio_channel port = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
> +
> + /* Program Tx lane resets to default */
> + mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> + DPIO_PCS_TX_LANE2_RESET |
> + DPIO_PCS_TX_LANE1_RESET);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> + DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> + DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> + (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> + DPIO_PCS_CLK_SOFT_RESET);
> +
> + /* Fix up inter-pair skew failure */
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9386772..f0c21e4 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1621,35 +1621,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>
> static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> {
> - struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc =
> - to_intel_crtc(encoder->base.crtc);
> - enum dpio_channel port = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
> -
> intel_hdmi_prepare(encoder);
>
> - /* Program Tx lane resets to default */
> - mutex_lock(&dev_priv->sb_lock);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> - DPIO_PCS_TX_LANE2_RESET |
> - DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> - DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> - DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> - (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> - DPIO_PCS_CLK_SOFT_RESET);
> -
> - /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_phy_pre_pll_enable(encoder);
> }
>
> static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> --
> 2.4.11
>
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