On Mon, Apr 04, 2016 at 06:17:16PM -0300, Paulo Zanoni wrote:
> The DDX driver changes its behavior depending on the value it reads
> from i915.enable_fbc, so sanitize the value in order to allow it to
> know what's going on. It uses this in order to choose the defaults for
> the TearFree option. Before this patch, it will read -1 and always
> assume that FBC is disabled, so it won't force TearFree.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++--------
> 1 file changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index fc3c094..3d84ce3 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -824,21 +824,14 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
> struct intel_fbc *fbc = &dev_priv->fbc;
> - bool enable_by_default = IS_HASWELL(dev_priv) ||
> - IS_BROADWELL(dev_priv);
>
> if (intel_vgpu_active(dev_priv->dev)) {
> fbc->no_fbc_reason = "VGPU is active";
> return false;
> }
>
> - if (i915.enable_fbc < 0 && !enable_by_default) {
> - fbc->no_fbc_reason = "disabled per chip default";
> - return false;
> - }
> -
> if (!i915.enable_fbc) {
> - fbc->no_fbc_reason = "disabled per module param";
> + fbc->no_fbc_reason = "disabled per module param or by default";
> return false;
> }
>
> @@ -1240,6 +1233,16 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
> fbc->active = false;
> fbc->work.scheduled = false;
>
> + /* The DDX driver changes its behavior depending on the value it reads
> + * from i915.enable_fbc, so sanitize the value in order to allow it to
> + * know what's going on. */
> + if (i915.enable_fbc < 0) {
> + i915.enable_fbc = IS_HASWELL(dev_priv) ||
> + IS_BROADWELL(dev_priv);
> + DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
> + i915.enable_fbc);
> + }
Standard practice would be to call intel_sanitize_fbc().
i915.enable_fbc = intel_sanitize_fbc(dev_priv);
if (!i915.enable_fbc))
> fbc->no_fbc_reason = "unsupported by this chipset";
> return;
}
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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