On Wed, Apr 06, 2016 at 01:28:25PM +0300, Ville Syrjälä wrote: > On Tue, Apr 05, 2016 at 02:55:51PM -0700, Matt Roper wrote: > > On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote: > > > intel_update_max_cdclk() doesn't have a switch case for Broxton, so > > > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're > > > currently running at (e.g., 144 MHz) rather than the true maximum. This > > > causes our max dotclock to also be set too low and in turn leads mode > > > verification to reject perfectly valid modes while loading EDID firmware > > > blobs. > > > > > > Cc: Imre Deak <imre.deak@xxxxxxxxx> > > > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > > > --- > > > > One thing I should have mentioned is that it's unclear to me whether we > > should be looking at the cdclk limit bits in the DFSM register like we > > do on SKL/KBL. The bspec seems to indicate that the register in general > > applies to gen9, including BXT, but the actual meaning of the bits > > doesn't match up with the frequencies we have on BXT. > > It also says > "This field is unused on BXT. Any CD clock frequency limitation must be > done in software." > > Anyway the DFSM story is apparently a sad one. See the discussion eg. in > https://lists.freedesktop.org/archives/intel-gfx/2016-February/087510.html > would be nice if someone could pick that up and figure out what we really > want/need to do. Oh strange; the note about being unused for BXT gets hidden if you're filtering the bspec on BXT. I have to remove the filter to see it. Seems a bit backwards... Thanks for the confirmation and background. Matt > > > > > > > Matt > > > > > drivers/gpu/drm/i915/intel_display.c | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > index af74cdb..924d851 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct drm_device *dev) > > > dev_priv->max_cdclk_freq = 450000; > > > else > > > dev_priv->max_cdclk_freq = 337500; > > > + } else if (IS_BROXTON(dev)) { > > > + dev_priv->max_cdclk_freq = 624000; > > > } else if (IS_BROADWELL(dev)) { > > > /* > > > * FIXME with extra cooling we can allow > > > -- > > > 2.1.4 > > > > > > > -- > > Matt Roper > > Graphics Software Engineer > > IoTG Platform Enabling & Development > > Intel Corporation > > (916) 356-2795 > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
