On Tue, Mar 22, 2016 at 02:10:47AM -0700, Deak, Imre wrote: > On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote: > > For BXT, description of polarities of PORT_PLL_REF_SEL > > has been reversed for newer Gen9LP steppings according to the > > recent update in Bspec. This bit now should be set for > > "Non-SSC" mode for all Gen9LP starting from B0 stepping. > > > > v2: Only B0 and newer stepping should be affected by this > > change. > > What is this stepping information based on? It's not in BSpec, could > you file a change request to get it added there? > > --Imre That information is actually missing in Bspec and has to be added. I got this info from the owner of the HSD sighting directly. I will file a change request in Bspec. > > > > > Signed-off-by: Dongwon Kim <dongwon.kim@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > > index 4b636c4..c84589e 100644 > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > > @@ -1285,7 +1285,15 @@ static void bxt_ddi_pll_enable(struct > > drm_i915_private *dev_priv, > > enum port port = (enum port)pll->id; /* 1:1 port->PLL > > mapping */ > > > > temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); > > - temp &= ~PORT_PLL_REF_SEL; > > + /* > > + * Definition of each bit polarity has been changed > > + * after A1 stepping > > + */ > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) > > + temp &= ~PORT_PLL_REF_SEL; > > + else > > + temp |= PORT_PLL_REF_SEL; > > + > > /* Non-SSC reference */ > > I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); > > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
