On Mon, Mar 14, 2016 at 03:11:02PM +0000, Peter Antoine wrote: > Allow for the MOCS to be programmed for all engines. > Currently we program the MOCS when the first render batch > goes through. This works on most platforms but fails on > platforms that do not run a render batch early, > i.e. headless servers. The patch now programs all initialised engines > on init and the RCS is programmed again within the initial batch. This > is done for predictable consistency with regards to the hardware > context. > > Hardware context loading sets the values of the MOCS for RCS > and L3CC. Programming them from within the batch makes sure that > the render context is valid, no matter what the previous state of > the saved-context was. > > v2: posted correct version to the mailing list. > v3: moved programming to within engine->init_hw() (Chris Wilson) > v4: code formatting and white-space changes. (Chris Wilson) > > Signed-off-by: Peter Antoine <peter.antoine@xxxxxxxxx> So testcase? Execute a bunch of MI_STORE_REGISTER_MEM on the various rings in a fresh context each time and confirm the ABI for the first N locations. Repeat across suspend/resume (i.e. make sure the context image maintain the register state). Then verify that freshly constructed contexts also have the correct settings after resume. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
