On to, 2016-02-18 at 21:54 +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > PIPESTAT registers live in the display power well on VLV/CHV, so we > shouldn't access them when things are powered down. Let's check > whether the display interrupts are on or off before accessing the > PIPESTAT registers. > > Another option would be to read the PIPESTAT registers only when > the IIR register indicates that there's a pending pipe event. But > that would mean we might miss even more underrun reports than we > do now, because the underrun status bit lives in PIPESTAT but doesn't > actually generate an interrupt. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93738 > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Tested-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx> Btw, I think gen8_de_irq_handler would need to be fixed too for example by using display_irqs_enabled there as well. > --- > drivers/gpu/drm/i915/i915_irq.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c > index 25a89373df63..d56c261ad867 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1651,6 +1651,12 @@ static void > valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) > int pipe; > > spin_lock(&dev_priv->irq_lock); > + > + if (!dev_priv->display_irqs_enabled) { > + spin_unlock(&dev_priv->irq_lock); > + return; > + } > + > for_each_pipe(dev_priv, pipe) { > i915_reg_t reg; > u32 mask, iir_bit = 0; _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
