On Wed, Feb 03, 2016 at 02:59:11PM +0200, Mika Kahola wrote:
> On Wed, 2016-02-03 at 11:28 +0200, Jani Nikula wrote:
> > On Tue, 02 Feb 2016, Ramalingam C <ramalingam.c@xxxxxxxxx> wrote:
> > > We need to enable DSI PLL before configuring the DSI registers.
> > >
> > > Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/intel_dsi.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > > index 91cef35..378f879 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > @@ -478,8 +478,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> > >
> > > DRM_DEBUG_KMS("\n");
> > >
> > > - intel_dsi_prepare(encoder);
> > > intel_enable_dsi_pll(encoder);
> > > + intel_dsi_prepare(encoder);
> >
> > I'd really like to have this tested on BYT/CHV DSI to ensure we're not
> > breaking anything.
> >
> > BR,
> > Jani.
> >
> We have CI results for this. Should we be worried about CPU fifo
> underrun?
>
> http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1344/
Known issue on ilk: https://bugs.freedesktop.org/show_bug.cgi?id=93787
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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