Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> By using the same address for storing the HWS on every platform, we can
> remove the platform specific vfuncs and reduce the get-seqno routine to
> a single read of a cached memory location.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 10 ++--
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_trace.h | 2 +-
> drivers/gpu/drm/i915/intel_breadcrumbs.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 46 ++---------------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 86 ++++++++------------------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +--
> 9 files changed, 43 insertions(+), 122 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d09e48455dcb..5a706c700684 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -600,7 +600,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
> ring->name,
> i915_gem_request_get_seqno(work->flip_queued_req),
> dev_priv->next_seqno,
> - ring->get_seqno(ring),
> + intel_ring_get_seqno(ring),
> i915_gem_request_completed(work->flip_queued_req));
> } else
> seq_printf(m, "Flip not associated with any ring\n");
> @@ -732,10 +732,8 @@ static void i915_ring_seqno_info(struct seq_file *m,
> {
> struct rb_node *rb;
>
> - if (ring->get_seqno) {
> - seq_printf(m, "Current sequence (%s): %x\n",
> - ring->name, ring->get_seqno(ring));
> - }
> + seq_printf(m, "Current sequence (%s): %x\n",
> + ring->name, intel_ring_get_seqno(ring));
>
> spin_lock(&ring->breadcrumbs.lock);
> for (rb = rb_first(&ring->breadcrumbs.waiters);
> @@ -1355,7 +1353,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
>
> for_each_ring(ring, dev_priv, i) {
> acthd[i] = intel_ring_get_active_head(ring);
> - seqno[i] = ring->get_seqno(ring);
> + seqno[i] = intel_ring_get_seqno(ring);
> }
>
> i915_get_extra_instdone(dev, instdone);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 44d46018ee13..fcedcbc50834 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2971,13 +2971,13 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
>
> static inline bool i915_gem_request_started(struct drm_i915_gem_request *req)
> {
> - return i915_seqno_passed(req->ring->get_seqno(req->ring),
> + return i915_seqno_passed(intel_ring_get_seqno(req->ring),
> req->previous_seqno);
> }
>
> static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req)
> {
> - return i915_seqno_passed(req->ring->get_seqno(req->ring),
> + return i915_seqno_passed(intel_ring_get_seqno(req->ring),
> req->seqno);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 01d0206ca4dd..3e137fc701cf 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -903,7 +903,7 @@ static void i915_record_ring_state(struct drm_device *dev,
> ering->waiting = intel_engine_has_waiter(ring);
> ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
> ering->acthd = intel_ring_get_active_head(ring);
> - ering->seqno = ring->get_seqno(ring);
> + ering->seqno = intel_ring_get_seqno(ring);
> ering->start = I915_READ_START(ring);
> ering->head = I915_READ_HEAD(ring);
> ering->tail = I915_READ_TAIL(ring);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d73669783045..627c7fb6aa9b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2903,7 +2903,7 @@ static int semaphore_passed(struct intel_engine_cs *ring)
> if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
> return -1;
>
> - if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
> + if (i915_seqno_passed(intel_ring_get_seqno(signaller), seqno))
> return 1;
>
> /* cursory check for an unkickable deadlock */
> @@ -3068,7 +3068,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> semaphore_clear_deadlocks(dev_priv);
>
> acthd = intel_ring_get_active_head(ring);
> - seqno = ring->get_seqno(ring);
> + seqno = intel_ring_get_seqno(ring);
>
> if (ring->hangcheck.seqno == seqno) {
> if (ring_idle(ring, seqno)) {
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index cfb5f78a6e84..efca75bcace3 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -573,7 +573,7 @@ TRACE_EVENT(i915_gem_request_notify,
> TP_fast_assign(
> __entry->dev = ring->dev->primary->index;
> __entry->ring = ring->id;
> - __entry->seqno = ring->get_seqno(ring);
> + __entry->seqno = intel_ring_get_seqno(ring);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u",
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index 10b0add54acf..f66acf820c40 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -127,7 +127,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
> struct intel_wait *wait)
> {
> struct intel_breadcrumbs *b = &engine->breadcrumbs;
> - u32 seqno = engine->get_seqno(engine);
> + u32 seqno = intel_ring_get_seqno(engine);
> struct rb_node **p, *parent, *completed;
> bool first;
>
> @@ -269,7 +269,7 @@ void intel_engine_remove_wait(struct intel_engine_cs *engine,
> * the first_waiter. This is undesirable if that
> * waiter is a high priority task.
> */
> - u32 seqno = engine->get_seqno(engine);
> + u32 seqno = intel_ring_get_seqno(engine);
> while (i915_seqno_passed(seqno,
> to_wait(next)->seqno)) {
> struct rb_node *n = rb_next(next);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 333e95bda78a..ad51b1fc37cd 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1775,16 +1775,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> return 0;
> }
>
> -static u32 gen8_get_seqno(struct intel_engine_cs *ring)
> -{
> - return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
> -}
> -
> -static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
> -{
> - intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
> -}
> -
> static void bxt_seqno_barrier(struct intel_engine_cs *ring)
> {
> /*
> @@ -1800,14 +1790,6 @@ static void bxt_seqno_barrier(struct intel_engine_cs *ring)
> intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
> }
>
> -static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
> -{
> - intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
> -
> - /* See bxt_a_get_seqno() explaining the reason for the clflush. */
> - intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
> -}
> -
> static int gen8_emit_request(struct drm_i915_gem_request *request)
> {
> struct intel_ringbuffer *ringbuf = request->ringbuf;
> @@ -1832,7 +1814,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
> (ring->status_page.gfx_addr +
> (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
> intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
> + intel_logical_ring_emit(ringbuf, request->seqno);
> intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
> intel_logical_ring_emit(ringbuf, MI_NOOP);
> intel_logical_ring_advance_and_submit(request);
> @@ -2002,12 +1984,8 @@ static int logical_render_ring_init(struct drm_device *dev)
> ring->init_hw = gen8_init_render_ring;
> ring->init_context = gen8_init_rcs_context;
> ring->cleanup = intel_fini_pipe_control;
> - ring->get_seqno = gen8_get_seqno;
> - ring->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> ring->irq_seqno_barrier = bxt_seqno_barrier;
> - ring->set_seqno = bxt_a_set_seqno;
> - }
> ring->emit_request = gen8_emit_request;
> ring->emit_flush = gen8_emit_flush_render;
> ring->irq_get = gen8_logical_ring_get_irq;
> @@ -2053,12 +2031,8 @@ static int logical_bsd_ring_init(struct drm_device *dev)
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
>
> ring->init_hw = gen8_init_common_ring;
> - ring->get_seqno = gen8_get_seqno;
> - ring->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> ring->irq_seqno_barrier = bxt_seqno_barrier;
> - ring->set_seqno = bxt_a_set_seqno;
> - }
> ring->emit_request = gen8_emit_request;
> ring->emit_flush = gen8_emit_flush;
> ring->irq_get = gen8_logical_ring_get_irq;
> @@ -2082,8 +2056,6 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
>
> ring->init_hw = gen8_init_common_ring;
> - ring->get_seqno = gen8_get_seqno;
> - ring->set_seqno = gen8_set_seqno;
> ring->emit_request = gen8_emit_request;
> ring->emit_flush = gen8_emit_flush;
> ring->irq_get = gen8_logical_ring_get_irq;
> @@ -2107,12 +2079,8 @@ static int logical_blt_ring_init(struct drm_device *dev)
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
>
> ring->init_hw = gen8_init_common_ring;
> - ring->get_seqno = gen8_get_seqno;
> - ring->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> ring->irq_seqno_barrier = bxt_seqno_barrier;
> - ring->set_seqno = bxt_a_set_seqno;
> - }
> ring->emit_request = gen8_emit_request;
> ring->emit_flush = gen8_emit_flush;
> ring->irq_get = gen8_logical_ring_get_irq;
> @@ -2136,12 +2104,8 @@ static int logical_vebox_ring_init(struct drm_device *dev)
> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
>
> ring->init_hw = gen8_init_common_ring;
> - ring->get_seqno = gen8_get_seqno;
> - ring->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> ring->irq_seqno_barrier = bxt_seqno_barrier;
> - ring->set_seqno = bxt_a_set_seqno;
> - }
> ring->emit_request = gen8_emit_request;
> ring->emit_flush = gen8_emit_flush;
> ring->irq_get = gen8_logical_ring_get_irq;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 57ec21c5b1ab..c86d0e17d785 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1216,19 +1216,17 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> return ret;
>
> for_each_ring(waiter, dev_priv, i) {
> - u32 seqno;
> u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> - seqno = i915_gem_request_get_seqno(signaller_req);
> intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
> intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
> PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_FLUSH_ENABLE);
> intel_ring_emit(signaller, lower_32_bits(gtt_offset));
> intel_ring_emit(signaller, upper_32_bits(gtt_offset));
> - intel_ring_emit(signaller, seqno);
> + intel_ring_emit(signaller, signaller_req->seqno);
> intel_ring_emit(signaller, 0);
> intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
> MI_SEMAPHORE_TARGET(waiter->id));
> @@ -1257,18 +1255,16 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> return ret;
>
> for_each_ring(waiter, dev_priv, i) {
> - u32 seqno;
> u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> - seqno = i915_gem_request_get_seqno(signaller_req);
> intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
> MI_FLUSH_DW_OP_STOREDW);
> intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
> MI_FLUSH_DW_USE_GTT);
> intel_ring_emit(signaller, upper_32_bits(gtt_offset));
> - intel_ring_emit(signaller, seqno);
> + intel_ring_emit(signaller, signaller_req->seqno);
> intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
> MI_SEMAPHORE_TARGET(waiter->id));
> intel_ring_emit(signaller, 0);
> @@ -1299,11 +1295,9 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
>
> if (i915_mmio_reg_valid(mbox_reg)) {
> - u32 seqno = i915_gem_request_get_seqno(signaller_req);
> -
> intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit_reg(signaller, mbox_reg);
> - intel_ring_emit(signaller, seqno);
> + intel_ring_emit(signaller, signaller_req->seqno);
> }
> }
>
> @@ -1338,7 +1332,7 @@ gen6_add_request(struct drm_i915_gem_request *req)
>
> intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> - intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> + intel_ring_emit(ring, req->seqno);
> intel_ring_emit(ring, MI_USER_INTERRUPT);
> __intel_ring_advance(ring);
>
> @@ -1440,7 +1434,9 @@ static int
> pc_render_add_request(struct drm_i915_gem_request *req)
> {
> struct intel_engine_cs *ring = req->ring;
> - u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 addr = req->ring->status_page.gfx_addr +
> + (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> + u32 scratch_addr = addr;
> int ret;
>
> /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
> @@ -1455,11 +1451,12 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> - PIPE_CONTROL_WRITE_FLUSH |
> - PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
> - intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> - intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> + intel_ring_emit(ring,
> + GFX_OP_PIPE_CONTROL(4) |
> + PIPE_CONTROL_QW_WRITE |
> + PIPE_CONTROL_WRITE_FLUSH);
Why no more PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE?
-Mika
> + intel_ring_emit(ring, addr | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(ring, req->seqno);
> intel_ring_emit(ring, 0);
> PIPE_CONTROL_FLUSH(ring, scratch_addr);
> scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
> @@ -1473,12 +1470,12 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> scratch_addr += 2 * CACHELINE_BYTES;
> PIPE_CONTROL_FLUSH(ring, scratch_addr);
>
> - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) |
> + PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_WRITE_FLUSH |
> - PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
> PIPE_CONTROL_NOTIFY);
> - intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> - intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> + intel_ring_emit(ring, addr | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(ring, req->seqno);
> intel_ring_emit(ring, 0);
> __intel_ring_advance(ring);
>
> @@ -1506,30 +1503,6 @@ gen6_seqno_barrier(struct intel_engine_cs *ring)
> intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
> }
>
> -static u32
> -ring_get_seqno(struct intel_engine_cs *ring)
> -{
> - return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
> -}
> -
> -static void
> -ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
> -{
> - intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
> -}
> -
> -static u32
> -pc_render_get_seqno(struct intel_engine_cs *ring)
> -{
> - return ring->scratch.cpu_page[0];
> -}
> -
> -static void
> -pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
> -{
> - ring->scratch.cpu_page[0] = seqno;
> -}
> -
> static bool
> gen5_ring_get_irq(struct intel_engine_cs *ring)
> {
> @@ -1665,7 +1638,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
>
> intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> - intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> + intel_ring_emit(ring, req->seqno);
> intel_ring_emit(ring, MI_USER_INTERRUPT);
> __intel_ring_advance(ring);
>
> @@ -2457,7 +2430,10 @@ void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
> I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
> }
>
> - ring->set_seqno(ring, seqno);
> + intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
> + if (ring->irq_seqno_barrier)
> + ring->irq_seqno_barrier(ring);
> +
> ring->hangcheck.seqno = seqno;
> }
>
> @@ -2695,8 +2671,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen8_ring_put_irq;
> ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> ring->irq_seqno_barrier = gen6_seqno_barrier;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> if (i915_semaphore_is_enabled(dev)) {
> WARN_ON(!dev_priv->semaphore_obj);
> ring->semaphore.sync_to = gen8_ring_sync;
> @@ -2713,8 +2687,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen6_ring_put_irq;
> ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> ring->irq_seqno_barrier = gen6_seqno_barrier;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> if (i915_semaphore_is_enabled(dev)) {
> ring->semaphore.sync_to = gen6_ring_sync;
> ring->semaphore.signal = gen6_signal;
> @@ -2739,8 +2711,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> } else if (IS_GEN5(dev)) {
> ring->add_request = pc_render_add_request;
> ring->flush = gen4_render_ring_flush;
> - ring->get_seqno = pc_render_get_seqno;
> - ring->set_seqno = pc_render_set_seqno;
> ring->irq_get = gen5_ring_get_irq;
> ring->irq_put = gen5_ring_put_irq;
> ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
> @@ -2751,8 +2721,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->flush = gen2_render_ring_flush;
> else
> ring->flush = gen4_render_ring_flush;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> if (IS_GEN2(dev)) {
> ring->irq_get = i8xx_ring_get_irq;
> ring->irq_put = i8xx_ring_put_irq;
> @@ -2828,8 +2796,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->flush = gen6_bsd_ring_flush;
> ring->add_request = gen6_add_request;
> ring->irq_seqno_barrier = gen6_seqno_barrier;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> if (INTEL_INFO(dev)->gen >= 8) {
> ring->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
> @@ -2867,8 +2833,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->mmio_base = BSD_RING_BASE;
> ring->flush = bsd_ring_flush;
> ring->add_request = i9xx_add_request;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> if (IS_GEN5(dev)) {
> ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> ring->irq_get = gen5_ring_get_irq;
> @@ -2901,8 +2865,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
> ring->flush = gen6_bsd_ring_flush;
> ring->add_request = gen6_add_request;
> ring->irq_seqno_barrier = gen6_seqno_barrier;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> ring->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
> ring->irq_get = gen8_ring_get_irq;
> @@ -2932,8 +2894,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->flush = gen6_ring_flush;
> ring->add_request = gen6_add_request;
> ring->irq_seqno_barrier = gen6_seqno_barrier;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
> if (INTEL_INFO(dev)->gen >= 8) {
> ring->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
> @@ -2990,8 +2950,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->flush = gen6_ring_flush;
> ring->add_request = gen6_add_request;
> ring->irq_seqno_barrier = gen6_seqno_barrier;
> - ring->get_seqno = ring_get_seqno;
> - ring->set_seqno = ring_set_seqno;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> ring->irq_enable_mask =
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 3b49726b1732..28ab07b38c05 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -220,9 +220,6 @@ struct intel_engine_cs {
> * monotonic, even if not coherent.
> */
> void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
> - u32 (*get_seqno)(struct intel_engine_cs *ring);
> - void (*set_seqno)(struct intel_engine_cs *ring,
> - u32 seqno);
> int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
> u64 offset, u32 length,
> unsigned dispatch_flags);
> @@ -502,6 +499,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
> int intel_init_vebox_ring_buffer(struct drm_device *dev);
>
> u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
> +static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
> +{
> + return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
> +}
>
> int init_workarounds_ring(struct intel_engine_cs *ring);
>
> --
> 2.7.0.rc3
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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