Original value of 32 blocks is not sufficient when using cursor size of 256x256 causing FIFO underruns when the reworked wm caluclations in commit 024c9045221fe45482863c47c4b4c47d37f97cbf Author: Matt Roper <matthew.d.roper@xxxxxxxxx> Date: Thu Sep 24 15:53:11 2015 -0700 drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v4) are used. Increasing the number of blocks to 52 to make cursor plane tolerate SAGV block time for the maximum possible cursor size. v2: Included Matt's suggestion, bumping up the no of blocks in multi-pipe case to 16. Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx> Signed-off-by: Kalyan Kondapally <kalyan.kondapally@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d385d99..c5ba4e5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2802,9 +2802,9 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) { if (config->num_pipes_active == 1) - return 32; + return 52; - return 8; + return 16; } static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx