On Mon, Dec 14, 2015 at 10:15:53PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Several factors conspire against us when trying to execute > the tiled small-bo tests: > - pre-gen4 require power of two fences, with natural alignment > - the entire gtt may be mappable > - we put a guard page at the end of gtt > > What all that means is that when we try to use a tiled object half > the size of the mappable area, we can only fit it in the first half > of the gtt. That leads to a SIGBUS when we try to fault in the > object when there's already something (eg. fbdev) occupying the > first half of gtt. > > So in order to make the tests run on old machines, let's further > halve the object size when things look too tight. That defeats the point of the test. The idea is to have the two objects that just don't fit, but only just. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
