From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Several factors conspire against us when trying to execute the tiled small-bo tests: - pre-gen4 require power of two fences, with natural alignment - the entire gtt may be mappable - we put a guard page at the end of gtt What all that means is that when we try to use a tiled object half the size of the mappable area, we can only fit it in the first half of the gtt. That leads to a SIGBUS when we try to fault in the object when there's already something (eg. fbdev) occupying the first half of gtt. So in order to make the tests run on old machines, let's further halve the object size when things look too tight. Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- tests/gem_mmap_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/gem_mmap_gtt.c b/tests/gem_mmap_gtt.c index 3a64a6fdc342..5c3bafcc38ba 100644 --- a/tests/gem_mmap_gtt.c +++ b/tests/gem_mmap_gtt.c @@ -280,6 +280,18 @@ test_huge_bo(int fd, int huge, int tiling) switch (huge) { case -1: size = gem_mappable_aperture_size() / 2; + + /* Power of two fence size, natural fence + * alignment, and the guard page at the end + * gtt means that if the entire gtt is + * mappable, we can't usually fit in a tiled + * object half the size of the gtt. Let's use + * a quarter size one instead. + */ + if (tiling && + intel_gen(intel_get_drm_devid(fd)) < 4 && + size >= gem_aperture_size(fd) / 2) + size /= 2; break; case 0: size = gem_mappable_aperture_size() + PAGE_SIZE; -- 2.4.10 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx