On Tue, Nov 24, 2015 at 03:14:23PM +0100, Daniel Vetter wrote: > On Mon, Nov 23, 2015 at 02:42:21PM +0000, Chris Wilson wrote: > > On Mon, Nov 23, 2015 at 04:10:32PM +0200, Ville Syrjälä wrote: > > > On Sat, Nov 21, 2015 at 10:49:04AM +0000, Chris Wilson wrote: > > > > On Fri, Nov 20, 2015 at 10:09:20PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > > > > > To get a better idea if underruns occurred during crtc disabling, > > > > > let's check for them explicitly. This helps in cases where the > > > > > error interrupt isn't active, or there is no underrun interrupt > > > > > support at all. > > > > > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > > > Would this be better the vblank after enabling? > > > > > > We do that too. > > > > Oh, crtc disabling. I can't read. > > Hm, should we also double-check before disabling, to catch anything that > happened right before the modeset and avoid confusing it with underruns > happening during the modeset? Hmm. Yeah that might be a decent idea. Although we don't wait for the planes to be disabled before we disable the pipe so in theory some weird underrun stemming from the plane disable might still get mixed in there. > > But this is a good idea already. > > Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
