On ke, 2015-11-04 at 19:24 +0200, Imre Deak wrote: > Atm we toggle HW resources handled automatically by the DMC firmware. > This is redundant and also interferes with the firmware's functionality. > This patchset fixes this and also an old existing issue leaving RPM > disabled all the time (see Damien's patch). > > The patchset depends on Mika's firmware version blacklisting/capture > [1] and Animesh' firmware loading redesign [2] patchset. Both of these > are reviewed now. > > This patchset also relates to Patrik's DC5/DC6 rework patchset [3], but > it's not dependent on it. After discussing with him on IRC I'd suggest the > following merge order: > > Patchset [1], patchset [2], Patrik's firmware programming fix from > his patchset [4], this patchset, the rest of Patrik's patchset [3]. Feel > free to suggest a different order. > > I tested this on top of [1], [2], [4] on SKL-Y with eDP and DP outputs, > DC5/6, PC9/10 residencies and S3/S4 suspend/resume seemed to work as > expected. The basic D3 igt tests are also passing, as claimed by > Damien's patch. I pushed the series to dinq, thanks for the review. > > [1] > http://lists.freedesktop.org/archives/intel-gfx/2015-October/078898.html > > [2] > http://lists.freedesktop.org/archives/intel-gfx/2015-October/079041.html > > [3] > http://lists.freedesktop.org/archives/intel-gfx/2015-November/079343.html > > [4] > http://lists.freedesktop.org/archives/intel-gfx/2015-November/079349.html > > > Damien Lespiau (1): > drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini > sequences > > Imre Deak (9): > drm/i915: fix the power well ID for always on wells > drm/i915: fix lookup_power_well for power wells without any domain > drm/i915: rename intel_power_domains_resume to *_sync_hw > drm/i915/skl: init/uninit display core as part of the HW power domain > state > drm/i915/skl: don't toggle PW1 and MISC power wells on-demand > drm/i915/gen9: simplify DC toggling code > drm/i915/skl: disable DC states before display core init/uninit > drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLK > drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 > enabling > > drivers/gpu/drm/i915/i915_dma.c | 2 +- > drivers/gpu/drm/i915/i915_drv.c | 9 +- > drivers/gpu/drm/i915/i915_reg.h | 5 +- > drivers/gpu/drm/i915/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/intel_display.c | 24 +--- > drivers/gpu/drm/i915/intel_drv.h | 5 +- > drivers/gpu/drm/i915/intel_runtime_pm.c | 208 ++++++++++++++++++++------------ > 7 files changed, 149 insertions(+), 108 deletions(-) > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
