On Fri, 30 Oct 2015, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> On Fri, Oct 30, 2015 at 05:00:42PM +0100, Daniel Vetter wrote:
>> On Thu, Oct 29, 2015 at 09:26:02PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
>> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>> >
>> > Use intel_dp->DP in the eDP PLL setup, instead of doing RMWs.
>> >
>> > To do this we need to move DP_AUDIO_OUTPUT_ENABLE setup to happen later,
>> > so that we don't enable audio accidentally while configuring the PLL.
>> >
>> > Also intel_dp_link_down() must be made to update intel_dp->DP so that we
>> > don't re-enable the port by accident when turning off the PLL. This is
>> > safe now that we don't call intel_dp_link_down() during link retraining.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>> > ---
>> > drivers/gpu/drm/i915/intel_dp.c | 41 ++++++++++++++---------------------------
>> > 1 file changed, 14 insertions(+), 27 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> > index e259803..63659e7 100644
>> > --- a/drivers/gpu/drm/i915/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> > @@ -1548,23 +1548,18 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
>> > struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
>> > struct drm_device *dev = crtc->base.dev;
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > - u32 dpa_ctl;
>> >
>> > DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
>> > crtc->config->port_clock);
>> > - dpa_ctl = I915_READ(DP_A);
>> > - dpa_ctl &= ~DP_PLL_FREQ_MASK;
>> >
>> > - if (crtc->config->port_clock == 162000) {
>> > - dpa_ctl |= DP_PLL_FREQ_162MHZ;
>> > + intel_dp->DP &= ~DP_PLL_FREQ_MASK;
>> > +
>> > + if (crtc->config->port_clock == 162000)
>> > intel_dp->DP |= DP_PLL_FREQ_162MHZ;
>> > - } else {
>> > - dpa_ctl |= DP_PLL_FREQ_270MHZ;
>> > + else
>> > intel_dp->DP |= DP_PLL_FREQ_270MHZ;
>> > - }
>> > -
>> > - I915_WRITE(DP_A, dpa_ctl);
>> >
>> > + I915_WRITE(DP_A, intel_dp->DP);
>> > POSTING_READ(DP_A);
>> > udelay(500);
>> > }
>> > @@ -1613,9 +1608,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>> > intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
>> > intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
>> >
>> > - if (crtc->config->has_audio)
>> > - intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
>> > -
>> > /* Split out the IBX/CPU vs CPT settings */
>> >
>> > if (IS_GEN7(dev) && port == PORT_A) {
>> > @@ -2176,20 +2168,14 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
>> > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > - u32 dpa_ctl;
>> >
>> > assert_pipe_disabled(dev_priv, crtc->pipe);
>> > assert_dp_port_disabled(intel_dp);
>> > assert_edp_pll_disabled(dev_priv);
>> >
>> > DRM_DEBUG_KMS("\n");
>> > - dpa_ctl = I915_READ(DP_A);
>> > -
>> > - /* We don't adjust intel_dp->DP while tearing down the link, to
>> > - * facilitate link retraining (e.g. after hotplug). Hence clear all
>> > - * enable bits here to ensure that we don't enable too much. */
>> > - intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
>> > intel_dp->DP |= DP_PLL_ENABLE;
>> > +
>> > I915_WRITE(DP_A, intel_dp->DP);
>> > POSTING_READ(DP_A);
>> > udelay(200);
>> > @@ -2200,19 +2186,14 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
>> > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > - u32 dpa_ctl;
>> >
>> > assert_pipe_disabled(dev_priv, crtc->pipe);
>> > assert_dp_port_disabled(intel_dp);
>> > assert_edp_pll_enabled(dev_priv);
>> >
>> > - dpa_ctl = I915_READ(DP_A);
>> > + intel_dp->DP &= ~DP_PLL_ENABLE;
>>
>> I think we need to clear DP_AUDIO_OUTPUT_ENABLE here too, otherwise a dpms
>> off->on cycle will again enable audio too early in edp_pll_on.
>
> intel_dp_prepare() starts from scratch:
> "intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;"
Yeah, Daniel's point here is invalid.
For this part,
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
>>
>> >
>> > - /* We can't rely on the value tracked for the DP register in
>> > - * intel_dp->DP because link_down must not change that (otherwise link
>> > - * re-training will fail. */
>> > - dpa_ctl &= ~DP_PLL_ENABLE;
>> > - I915_WRITE(DP_A, dpa_ctl);
>> > + I915_WRITE(DP_A, intel_dp->DP);
>> > POSTING_READ(DP_A);
>> > udelay(200);
>> > }
>> > @@ -2568,6 +2549,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp)
>> > {
>> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > + struct intel_crtc *crtc =
>> > + to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
>> >
>> > /* enable with pattern 1 (as per spec) */
>> > _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
>> > @@ -2583,6 +2566,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp)
>> > * fail when the power sequencer is freshly used for this port.
>> > */
>> > intel_dp->DP |= DP_PORT_EN;
>> > + if (crtc->config->has_audio)
>> > + intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
>>
>> If I read the code correctly before this patch the I915_WRITE right above
>> this one here already enabled the audio bit. Shouldn't matter, and
>> probably better, but must be mentioned in the commit message.
>
> Indeed. The new order even makes more sense. I'll add a note.
>
>>
>> With these two things addressed:
>>
>> Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
>>
>> >
>> > I915_WRITE(intel_dp->output_reg, intel_dp->DP);
>> > POSTING_READ(intel_dp->output_reg);
>> > @@ -4028,6 +4013,8 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>> > }
>> >
>> > msleep(intel_dp->panel_power_down_delay);
>> > +
>> > + intel_dp->DP = DP;
>> > }
>> >
>> > static bool
>> > --
>> > 2.4.10
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Technology Center
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