On Thu, Nov 05, 2015 at 11:04:11PM +0200, Imre Deak wrote:
> The display power well support on this platform is in a somewhat broken
> state atm, so disable it by default.
>
> This in effect will get rid of incorrect assert WARNs about the CSR/DMC
> firmware not being loaded during power well toggling. It also removes a
> problem during driver loading where a register is accessed while its
> backing power well is down, resulting in another WARN. Until we come up
> with the root cause of the second problem and the proper fix for both
> issues, keep all display side power wells on.
>
> Also clarify a bit the option description.
>
> Reported-by: Dave Airlie <airlied@xxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Looks all right.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 +++--
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++++++++++++++
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index ca9b8f6..e950135 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = {
> .enable_ppgtt = -1,
> .enable_psr = 0,
> .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
> - .disable_power_well = 1,
> + .disable_power_well = -1,
> .enable_ips = 1,
> .prefault_disable = 0,
> .load_detect_test = 0,
> @@ -127,7 +127,8 @@ MODULE_PARM_DESC(preliminary_hw_support,
>
> module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0600);
> MODULE_PARM_DESC(disable_power_well,
> - "Disable the power well when possible (default: true)");
> + "Disable display power wells when possible"
> + "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");
>
> module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);
> MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ec010ee..14016f0 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1811,6 +1811,23 @@ static struct i915_power_well bxt_power_wells[] = {
> }
> };
>
> +static int
> +sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> + int disable_power_well)
> +{
> + if (disable_power_well >= 0)
> + return !!disable_power_well;
> +
> + if (IS_SKYLAKE(dev_priv)) {
> + DRM_DEBUG_KMS("Disabling display power well support\n");
> + return 0;
> + }
> +
> + return 1;
> +
> +
> +}
> +
> #define set_power_wells(power_domains, __power_wells) ({ \
> (power_domains)->power_wells = (__power_wells); \
> (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
> @@ -1827,6 +1844,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
>
> + i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
> + i915.disable_power_well);
> +
> mutex_init(&power_domains->lock);
>
> /*
> --
> 2.5.0
>
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--
Ville Syrjälä
Intel OTC
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