Use the new struct intel_dp_signal_levels to store voltage swing and pre emphasis levels for VLV. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_dp_signal_levels.c | 38 ++++++++++++++++++--------- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_signal_levels.c b/drivers/gpu/drm/i915/intel_dp_signal_levels.c index aedd35b..1d07f46 100644 --- a/drivers/gpu/drm/i915/intel_dp_signal_levels.c +++ b/drivers/gpu/drm/i915/intel_dp_signal_levels.c @@ -115,7 +115,7 @@ _dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) } } -static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) +static void vlv_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = dev->dev_private; @@ -124,7 +124,6 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) to_intel_crtc(dport->base.base.crtc); unsigned long demph_reg_value, preemph_reg_value, uniqtranscale_reg_value; - uint8_t train_set = intel_dp->train_set[0]; enum dpio_channel port = vlv_dport_to_channel(dport); int pipe = intel_crtc->pipe; @@ -149,7 +148,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) uniqtranscale_reg_value = 0x5598DA3A; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; case DP_TRAIN_PRE_EMPH_LEVEL_1: @@ -168,7 +168,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) uniqtranscale_reg_value = 0x55ADDA3A; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; case DP_TRAIN_PRE_EMPH_LEVEL_2: @@ -183,7 +184,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) uniqtranscale_reg_value = 0x55ADDA3A; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; case DP_TRAIN_PRE_EMPH_LEVEL_3: @@ -194,11 +196,13 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) uniqtranscale_reg_value = 0x55ADDA3A; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_PRE_EMPHASIS_MASK); + return; } mutex_lock(&dev_priv->sb_lock); @@ -211,10 +215,20 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); mutex_unlock(&dev_priv->sb_lock); - - return 0; } +static const struct signal_levels vlv_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_3, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_3, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = vlv_set_signal_levels, +}; + static bool chv_need_uniq_trans_scale(uint8_t train_set) { return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && @@ -582,8 +596,6 @@ _update_signal_levels(struct intel_dp *intel_dp) mask = DDI_BUF_EMP_MASK; } else if (IS_CHERRYVIEW(dev)) { signal_levels = chv_signal_levels(intel_dp); - } else if (IS_VALLEYVIEW(dev)) { - signal_levels = vlv_signal_levels(intel_dp); } else { WARN(1, "Should be calling intel_dp->signal_levels->set instead."); return; @@ -642,7 +654,9 @@ intel_dp_init_signal_levels(struct intel_dp *intel_dp) struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); enum port port = intel_dig_port->port; - if (IS_IVYBRIDGE(dev)) { + if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { + intel_dp->signal_levels = &vlv_signal_levels; + } else if (IS_IVYBRIDGE(dev)) { if (port == PORT_A) intel_dp->signal_levels = &ivb_edp_signal_levels; else -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx