On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote: > On 10/7/15, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote: > >> On 9/24/15, Nick Bowler <nbowler@xxxxxxxxxx> wrote: > >> > Testing out 4.3-rc2, first thing I notice is that the VGA output is > >> > not working. Specifically, the display is continuously powering on > >> > and off -- at no point is any image visible on the screen (I am > >> > expecting to see the console output). The display connected to the > >> > HDMI output is working fine. > [...] > >> b8afb9113c519a8bd742f7df8c424b0af69a75cd is the first bad commit > >> commit b8afb9113c519a8bd742f7df8c424b0af69a75cd > >> Author: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > >> Date: Mon Jun 29 15:25:48 2015 +0300 > >> > >> drm/i915: Keep GMCH DPLL VGA mode always disabled > [...] > > @@ -1790,13 +1790,13 @@ static void i9xx_disable_pll(struct intel_crtc > > *crtc) > > /* Make sure the pipe isn't still relying on us */ > > assert_pipe_disabled(dev_priv, pipe); > > > > - I915_WRITE(DPLL(pipe), 0); > > + I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); > > POSTING_READ(DPLL(pipe)); > > } > > > > > > That hunk is the only relevant part for your machine. Can you try to revert > > just that manually? > > > > But I'm really surprised that would have any effect since we only used > > to enable "VGA mode" when the DPLL is off. And when the DPLL is off, > > there's nothing on the screen anyway. > > Nevertheless, manually reverting just that hunk seems to fix it. Hmm. You said VGA has the problem, but HDMI does not. Was the problem happening even when you have both displays enabled at the same time, or just when VGA was enabled alone? I've attached two potential patches that might help. Can you give a try to just patch 1, and if that alone doesn't help then both patches together? -- Ville Syrjälä Intel OTC
>From 98cbf947740861f0e1bf625dfaedbd43be7746ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx> Date: Wed, 7 Oct 2015 18:23:26 +0300 Subject: [PATCH 1/2] restore DPLL write --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 147e700..f4fdff9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); } + I915_WRITE(reg, dpll); + /* Wait for the clocks to stabilize. */ POSTING_READ(reg); udelay(150); -- 2.4.9
>From 78ee4cbf2560891e59e6ae58fbcd197a34012819 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx> Date: Wed, 7 Oct 2015 18:27:33 +0300 Subject: [PATCH 2/2] enable VGA mode before P1/P2 write --- drivers/gpu/drm/i915/intel_display.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f4fdff9..036550f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1743,6 +1743,12 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); } + /* + * Apparently we need to have VGA mode enabled + * prior to writing P1/P2, otherwise they won't take. + */ + I915_WRITE(reg, 0); + I915_WRITE(reg, dpll); /* Wait for the clocks to stabilize. */ -- 2.4.9
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