On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
> Hi,
>
> This issue is still present in 4.3-rc4.
>
> On 9/24/15, Nick Bowler <nbowler@xxxxxxxxxx> wrote:
> > Testing out 4.3-rc2, first thing I notice is that the VGA output is
> > not working. Specifically, the display is continuously powering on
> > and off -- at no point is any image visible on the screen (I am expecting
> > to see the console output). The display connected to the HDMI output is
> > working fine.
> >
> > Linux 4.2 did not suffer from this problem.
> >
> > In dmesg I see the following messages, which I do not see on a working
> > kernel. Full dmesg from 4.3-rc2 is attached (gzipped).
> >
> > [ 0.115339] [drm:drm_calc_timestamping_constants] *ERROR* crtc
> > 21: Can't calculate constants, dotclock = 0!
> > [ 0.117582] [drm:intel_opregion_init] *ERROR* No ACPI video bus found
> >
> > This is an older machine with Intel G45 graphics.
>
> I was able to identify the commit which fixed my boot crashes, so I
> cherry-picked 80aa93128653 ("drm/i915: disable_shared_pll doesn't
> work on pre-gen5") on top of all otherwise untestable commits. This
> allowed bisection to proceed:
>
> b8afb9113c519a8bd742f7df8c424b0af69a75cd is the first bad commit
> commit b8afb9113c519a8bd742f7df8c424b0af69a75cd
> Author: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Date: Mon Jun 29 15:25:48 2015 +0300
>
> drm/i915: Keep GMCH DPLL VGA mode always disabled
>
> We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
> again when disabling the DPLL. Having VGA mode enabled even in unused
> DPLLs can cause problems for CHV, so it seems wiser to always keep it
> disabled. And let's just do that on all GMCH platforms to keep things
> as similar as possible between them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@xxxxxxxxx>
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
>
> :040000 040000 7797d596e73ecf75723375028decd25fbe332ee0
> 9f90a92eec483919853d68563bbb09a71a305532 M drivers
>
> Unfortunately it does not revert cleanly on master.
@@ -1790,13 +1790,13 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
/* Make sure the pipe isn't still relying on us */
assert_pipe_disabled(dev_priv, pipe);
- I915_WRITE(DPLL(pipe), 0);
+ I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
POSTING_READ(DPLL(pipe));
}
That hunk is the only relevant part for your machine. Can you try to revert
just that manually?
But I'm really surprised that would have any effect since we only used
to enable "VGA mode" when the DPLL is off. And when the DPLL is off,
there's nothing on the screen anyway.
--
Ville Syrjälä
Intel OTC
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