The same work-arond is applied per-context in
init_l3_partitioning_workarounds(), so the direct MMIO write of
GEN7_L3SQCREG1 should be redundant now. Applying the work-around at
context creation time also makes sure that the MMIO writes are not
accidentally undone by userspace.
Signed-off-by: Francisco Jerez <currojerez@xxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 6 ------
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 663bc8f..b445c93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5930,7 +5930,6 @@ enum skl_disp_power_wells {
#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
#define GEN7_L3SQCREG1 0xB010
-#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
#define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
#define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00D30000
#define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d495043..ccb91d3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6810,12 +6810,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
/*
- * WaIncreaseL3CreditsForVLVB0:vlv
- * This is the hardware default actually.
- */
- I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
-
- /*
* WaDisableVLVClockGating_VBIIssue:vlv
* Disable clock gating on th GCFG unit to prevent a delay
* in the reporting of vblank events.
--
2.5.1
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