On Fri, Sep 25, 2015 at 02:33:46PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping.
>
> Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d5fdbc8..2a33b9d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1019,11 +1019,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
> if (ret)
> return ret;
>
> - /* WaDisablePowerCompilerClockGating:skl */
> - if (INTEL_REVID(dev) == SKL_REVID_B0)
> - WA_SET_BIT_MASKED(HIZ_CHICKEN,
> - BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
> -
Yes. However Bspec shows this to be valid for BXT until B0. The register
description OTOH says SKL:B only, as does the w/a database. I'm too lazy
to start hsd trawling now, so maybe you can figure out what's going on there?
> if (INTEL_REVID(dev) <= SKL_REVID_D0) {
> /*
> *Use Force Non-Coherent whenever executing a 3D context. This
> --
> 1.9.1
>
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--
Ville Syrjälä
Intel OTC
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