On Sat, Sep 12, 2015 at 10:17:51AM +0530, Sagar Arun Kamble wrote: > WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be > disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0. > > v2: Added GT3/GT4 Check. > > Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1f6b5bb..c93d3a7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4853,11 +4853,14 @@ static void gen9_enable_rc6(struct drm_device *dev) > > /* > * 3b: Enable Coarse Power Gating only when RC6 is enabled. > - * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6. > + * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. > */ > - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? > - GEN9_MEDIA_PG_ENABLE : 0); > - > + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > + ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) I fixed up the continuation to be aligned properly while applying. -Daniel > + I915_WRITE(GEN9_PG_ENABLE, 0); > + else > + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? > + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
