> > > > + if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED > > && > > > > + ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % > > 4)) { > > > > + DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line > > aligned\n", > > > > + mode_cmd->offsets[1]); > > > > + return -EINVAL; > > > > + } > > > > > > I was going to say I can't find anything in the spec to support this, > > > but after some more reading I got it "The display hardware requires > > > that the UV surface start satisfies four line alignment from the > > > begining of the page." So the check should be something like > > > ((offsets[1] & 0xfff) / pitches[1] % 4. > > > > Ignore my previous response for this. Yes, above check should > check for 12-lsbs. Will update and respun shortly. Submitted updated patch. With this change, resolved all your feedback. Is there any more feedback? If not, can you issue R-B tag for the patches? _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx