This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
v3:
-cosmetic update, split checks into two (Ville)
Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84dad95..5433c6d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14349,9 +14349,40 @@ static int intel_framebuffer_init(struct drm_device *dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)->gen < 9) {
+ DRM_DEBUG("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd->offsets[1]) {
+ DRM_DEBUG("uv start offset not set\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->pitches[0] != mode_cmd->pitches[1]) {
+ DRM_DEBUG("y and uv subplanes have different pitches\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->handles[0] != mode_cmd->handles[1]) {
+ DRM_DEBUG("y and uv subplanes have different handles\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
+ (mode_cmd->offsets[1] & 0xFFF)) {
+ DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new tile-row\n",
+ mode_cmd->offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
+ ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % 4)) {
+ DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line aligned\n",
+ mode_cmd->offsets[1]);
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG("unsupported pixel format: %s\n",
- drm_get_format_name(mode_cmd->pixel_format));
+ drm_get_format_name(mode_cmd->pixel_format));
return -EINVAL;
}
--
1.7.9.5
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