This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)
v4:
-Rebased to current kernel version 4.2.0.rc4 (me)
v5:
-Used round up division for aux_stride calculation,
adjusted dst rect as part of macro pixel boundary calculation (Ville)
Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 59 ++++++++++++++++++++++++++++++++--
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 825d721..ae40b22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5602,6 +5602,31 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5433c6d..6714066 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,8 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -3094,6 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane->state);
@@ -3150,11 +3154,34 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
+ /*
+ * TBD: For NV12 90/270 rotation, Y and UV subplanes should
+ * be treated as separate surfaces and GTT remapping for
+ * rotation should be done separately for each subplane.
+ * Enable support once seperate remappings are available.
+ */
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) << 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+ /*
+ * If UV starts from middle of a page, then UV start should
+ * be programmed to beginning of that page. And offset into that
+ * page to be programmed into y-offset
+ */
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb->pitches[0] * (height_in_mem - tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */
+ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ?
+ DIV_ROUND_UP(stride, 2) : stride;
+ }
}
plane_offset = y_offset << 16 | x_offset;
@@ -3162,11 +3189,14 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | aux_x_offset);
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
WARN_ON(!dst_w || !dst_h);
+
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3175,6 +3205,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0);
} else {
+ WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
}
@@ -11627,12 +11658,36 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
bool turn_off, turn_on, visible, was_visible;
struct drm_framebuffer *fb = plane_state->fb;
+ struct intel_plane_state *intel_plane_state =
+ to_intel_plane_state(plane_state);
+
+ /* Adjust (macro)pixel boundary */
+ if (fb && intel_format_is_yuv(fb->pixel_format)) {
+ bool can_scale = false;
+
+ intel_plane_state->src.x1 &= ~0x10000;
+ intel_plane_state->src.x2 &= ~0x10000;
+
+ /* scaler use allowed when colorkey isn't requested */
+ if ((INTEL_INFO(dev)->gen >= 9) &&
+ (intel_plane_state->ckey.flags == I915_SET_COLORKEY_NONE))
+ can_scale = true;
+
+ /* Must keep src and dst the same if we can't scale. */
+ if (!can_scale) {
+ intel_plane_state->dst.x1 &= ~1;
+ intel_plane_state->dst.x2 &= ~1;
+ }
+
+ if (drm_rect_width(&intel_plane_state->dst) == 0)
+ intel_plane_state->visible = false;
+ }
if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
plane->type != DRM_PLANE_TYPE_CURSOR) {
ret = skl_update_scaler_plane(
to_intel_crtc_state(crtc_state),
- to_intel_plane_state(plane_state));
+ intel_plane_state);
if (ret)
return ret;
}
@@ -11646,7 +11701,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
intel_crtc->atomic.disabled_planes |= 1 << i;
was_visible = old_plane_state->visible;
- visible = to_intel_plane_state(plane_state)->visible;
+ visible = intel_plane_state->visible;
if (!was_crtc_enabled && WARN_ON(was_visible))
was_visible = false;
--
1.7.9.5
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