> > > > > > +
> > > > > > + /* workaround for NV12 */
> > > > > > + skl_wa_clkgate(dev_priv, pipe, 1);
> > > > >
> > > > > I wonder what's the cost of having this
> > > > > a) always enabled
> > > > > b) enabled when the pipe is enabled
> > > > > c) enabled only when NV12 is used
> > > > > ?
> > > >
> > > > Initially optimized to enable only when nv12 is used,
> > > > but there are some corner cases when planes switch to and
> > > > from nv12 to non-nv12 and SV recommendation is to enable
> > > > always; and SV evaluated cost, and it isn't a big concern.
> > >
> > > So, based on that we could just stuff it into init_clock_gating and
> > > forget about it.
> >
> > Couldn't include into init_clock_gating because this requires
> > a pipe based check.
>
> init_clock_gating()
> {
> ...
> enable for pipe A
> enable for pipe B
> ...
> }
>
> or
>
> for_each_pipe(pipe)
> if (pipe != C)
> enable w/a
>
Oh yeah, it can be done that way.
OK, will move it there.
>
> >
> > By the way, so far 4 patches got RB tags.
> > In the respun series (http://lists.freedesktop.org/archives/intel-gfx/2015-
> September/075235.html
> > addressed your feedback), those 4 tags goes to 1, 3, 5 and 8 of 15.
> > Can you check updated patches and issue R-B tags for remaining ones?
>
> I think your trigger finger is a bit overly sensitive :) We still had
> open issues in this series so posting another one makes things somewhat
> messy.
There is one other open relate to tile-Yf Y, UV plane pitch/stride check.
I just responded to that one.
>
> --
> Ville Syrjälä
> Intel OTC
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