> > > > +static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
> > > > + int pipe, int enable)
> > > > +{
> > > > + if (pipe == PIPE_A || pipe == PIPE_B) {
> > > > + if (enable)
> > > > + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > > > + DUPS1_GATING_DIS | DUPS2_GATING_DIS);
> > > > + else
> > > > + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > > > + I915_READ(CLKGATE_DIS_PSL(pipe) &
> > > > + ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
> > > > + }
> > > > +}
> > > > +
> > > > static void haswell_crtc_enable(struct drm_crtc *crtc)
> > > > {
> > > > struct drm_device *dev = crtc->dev;
> > > > @@ -5094,6 +5119,9 @@ static void haswell_crtc_enable(struct drm_crtc
> > > *crtc)
> > > > intel_wait_for_vblank(dev, hsw_workaround_pipe);
> > > > intel_wait_for_vblank(dev, hsw_workaround_pipe);
> > > > }
> > > > +
> > > > + /* workaround for NV12 */
> > > > + skl_wa_clkgate(dev_priv, pipe, 1);
> > >
> > > I wonder what's the cost of having this
> > > a) always enabled
> > > b) enabled when the pipe is enabled
> > > c) enabled only when NV12 is used
> > > ?
> >
> > Initially optimized to enable only when nv12 is used,
> > but there are some corner cases when planes switch to and
> > from nv12 to non-nv12 and SV recommendation is to enable
> > always; and SV evaluated cost, and it isn't a big concern.
>
> So, based on that we could just stuff it into init_clock_gating and
> forget about it.
Couldn't include into init_clock_gating because this requires
a pipe based check.
By the way, so far 4 patches got RB tags.
In the respun series (http://lists.freedesktop.org/archives/intel-gfx/2015-September/075235.html
addressed your feedback), those 4 tags goes to 1, 3, 5 and 8 of 15.
Can you check updated patches and issue R-B tags for remaining ones?
>
> But we'll run into problems as soon as render compression enters the
> picure. But I don't have a problem leaving it up to the render
> compression patches to solve.
>
> --
> Ville Syrjälä
> Intel OTC
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