On Wed, Aug 26, 2015 at 06:27:36PM +0300, Mika Kuoppala wrote: > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > Delay the expensive read on the FPGA_DBG register from once per mmio to > > once per forcewake section when we are doing the general wellbeing > > check rather than the targetted error detection. This almost reduces > > the overhead of the debug facility (for example when submitting execlists) > > to zero whilst keeping the debug checks around. > > > > v2: Enable one-shot mmio debugging from the interrupt check as well as a > > safeguard to catch invalid display writes from outside the powerwell. > > > > Not a particular problem with this patch, but I noticed that > on skl, we lose the concents of the FPGA_DBG register > immediately when we clear the forcewake. Without explicit > write to clear the bit, which is claimed to be sticky. > > On re aquiring forcewake, the register contents is zero :( Doesn't that defeat the purpose of using the dbg register to detect accesses outside of the powerwell? I'd ask whether the new behaviour is documented/intended... -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
