Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> Delay the expensive read on the FPGA_DBG register from once per mmio to
> once per forcewake section when we are doing the general wellbeing
> check rather than the targetted error detection. This almost reduces
> the overhead of the debug facility (for example when submitting execlists)
> to zero whilst keeping the debug checks around.
>
> v2: Enable one-shot mmio debugging from the interrupt check as well as a
> safeguard to catch invalid display writes from outside the powerwell.
>
Not a particular problem with this patch, but I noticed that
on skl, we lose the concents of the FPGA_DBG register
immediately when we clear the forcewake. Without explicit
write to clear the bit, which is claimed to be sticky.
On re aquiring forcewake, the register contents is zero :(
-Mika
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 56 ++++++++++++++++++++-----------------
> 1 file changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9d3c2e420d2b..05c50cc87d1d 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -149,6 +149,30 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> }
>
> static void
> +hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
> +{
> + static bool mmio_debug_once = true;
> +
> + if (i915.mmio_debug || !mmio_debug_once)
> + return;
> +
> + if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
> + DRM_DEBUG("Unclaimed register detected, "
> + "enabling oneshot unclaimed register reporting. "
> + "Please use i915.mmio_debug=N for more information.\n");
> + __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> + i915.mmio_debug = mmio_debug_once--;
> + }
> +}
> +
> +static void
> +fw_domains_put_debug(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
> +{
> + hsw_unclaimed_reg_detect(dev_priv);
> + fw_domains_put(dev_priv, fw_domains);
> +}
> +
> +static void
> fw_domains_posting_read(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore_forcewake_domain *d;
> @@ -623,23 +647,6 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
> }
> }
>
> -static void
> -hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
> -{
> - static bool mmio_debug_once = true;
> -
> - if (i915.mmio_debug || !mmio_debug_once)
> - return;
> -
> - if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
> - DRM_DEBUG("Unclaimed register detected, "
> - "enabling oneshot unclaimed register reporting. "
> - "Please use i915.mmio_debug=N for more information.\n");
> - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> - i915.mmio_debug = mmio_debug_once--;
> - }
> -}
> -
> #define GEN2_READ_HEADER(x) \
> u##x val = 0; \
> assert_device_not_suspended(dev_priv);
> @@ -891,7 +898,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
> gen6_gt_check_fifodbg(dev_priv); \
> } \
> hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> - hsw_unclaimed_reg_detect(dev_priv); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -933,7 +939,6 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
> __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
> __raw_i915_write##x(dev_priv, reg, val); \
> hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> - hsw_unclaimed_reg_detect(dev_priv); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -1182,6 +1187,10 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
> FORCEWAKE, FORCEWAKE_ACK);
> }
>
> + if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
> + dev_priv->uncore.funcs.force_wake_put == fw_domains_put)
> + dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
> +
> /* All future platforms are expected to require complex power gating */
> WARN_ON(dev_priv->uncore.fw_domains == 0);
> }
> @@ -1545,11 +1554,6 @@ bool intel_has_gpu_reset(struct drm_device *dev)
>
> void intel_uncore_check_errors(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
> - (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
> - DRM_ERROR("Unclaimed register before interrupt\n");
> - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> - }
> + if (HAS_FPGA_DBG_UNCLAIMED(dev))
> + hsw_unclaimed_reg_detect(to_i915(dev));
> }
> --
> 2.5.0
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